82bace6e0d
Config the sram0 to be non-cachable to PASS the DMA testcases chan_blen_transfer and loop_transfer on the stm32f746zg and stm32f767zi nucleo boards. The CONFIG_NOCACHE_MEMORY is useless as the memory region gets the NOCACHE ATTRibutes for stm32H7 or stm32F7 as well. Signed-off-by: Francois Ramu <francois.ramu@st.com>
8 lines
282 B
Text
8 lines
282 B
Text
CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=5
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CONFIG_DMA_LOOP_TRANSFER_NUMBER_OF_DMAS=2
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# Required by BDMA which only has access to
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# a NOCACHE SRAM4 section. All other DMAs also
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# has access to this section.
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CONFIG_CODE_DATA_RELOCATION=y
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CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM4"
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