8a47dd5ff8
Enable clock control by default on S32K344 SoCs and add clock definitions. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
82 lines
1.6 KiB
Text
82 lines
1.6 KiB
Text
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <1>;
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};
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <16>;
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};
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};
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soc {
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interrupt-parent = <&nvic>;
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itcm: memory@0 {
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compatible = "zephyr,memory-region", "arm,itcm";
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reg = <0x00000000 DT_SIZE_K(64)>;
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zephyr,memory-region = "ITCM";
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};
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dtcm: memory@20000000 {
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compatible = "zephyr,memory-region", "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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zephyr,memory-region = "DTCM";
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};
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sram0_1: sram0_1@20400000 {
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compatible = "mmio-sram";
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reg = <0x20400000 DT_SIZE_K(320)>;
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};
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/*
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* Last 48Kb is reserved by Secure BAF, application core cannot access it.
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*
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* Do not assign the compatible for this now, when Flash API is implemented,
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* need to check if "soc-nv-flash" can be used or a new binding need to be
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* created, based on it.
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*/
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flash0: flash@400000 {
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reg = <0x00400000 DT_SIZE_K(4048)>;
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status = "disabled";
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};
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clock: clock-controller@402c8000 {
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compatible = "nxp,s32-clock";
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reg = <0x402c8000 0x4000>,
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<0x402cc000 0x4000>,
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<0x402d0000 0x4000>,
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<0x402d4000 0x4000>,
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<0x402d8000 0x4000>,
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<0x402e0000 0x4000>;
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#clock-cells = <1>;
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status = "okay";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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