88f099c3a1
1. SW PWM device node added to common nrf5_common.dtsi 2. SW PWM node set in all nRF5x DTSI files. Different initial settings for nRF51 and nRF52 devices. Status is ok by default for nRF51. 3. Added yaml binding for Nordic SW PWM node. 4. Set codeowner of nordic dts bindings to @anangl Signed-off-by: Gaute Gamnes <gaute.gamnes@nordicsemi.no>
205 lines
3.9 KiB
Text
205 lines
3.9 KiB
Text
#include <arm/armv7-m.dtsi>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "nrf5_common.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4";
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reg = <0>;
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};
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};
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flash-controller@4001E000 {
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compatible = "nordic,nrf52-flash-controller";
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reg = <0x4001E000 0x550>;
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#address-cells = <1>;
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#size-cells = <1>;
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label="NRF_FLASH_DRV_NAME";
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "NRF_FLASH";
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write-block-size = <4>;
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};
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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};
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aliases {
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i2c-0 = &i2c0;
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spi-0 = &spi0;
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uart-0 = &uart0;
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adc-0 = &adc;
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gpio-0 = &gpio0;
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gpiote-0 = &gpiote;
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wdt-0 = &wdt;
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pwm-0 = &pwm0;
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qdec-0 = &qdec;
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rtc-0 = &rtc0;
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rtc-1 = &rtc1;
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timer-0 = &timer0;
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timer-1 = &timer1;
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timer-2 = &timer2;
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};
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soc {
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adc: adc@40007000 {
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compatible = "nordic,nrf-saadc";
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reg = <0x40007000 0x1000>;
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interrupts = <7 1>;
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status = "disabled";
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label = "ADC_0";
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};
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clock: clock@40000000 {
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compatible = "nordic,nrf-clock";
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reg = <0x40000000 0x1000>;
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interrupts = <0 1>;
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status = "ok";
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label = "CLOCK";
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};
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uart0: uart@40002000 {
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/* uart can be either UART or UARTE, for the user to pick */
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/* compatible = "nordic,nrf-uarte" or "nordic,nrf-uart"; */
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reg = <0x40002000 0x1000>;
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interrupts = <2 1>;
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status = "disabled";
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label = "UART_0";
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};
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gpiote: gpiote@40006000 {
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compatible = "nordic,nrf-gpiote";
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reg = <0x40006000 0x1000>;
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interrupts = <6 5>;
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status = "disabled";
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label = "GPIOTE_0";
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};
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gpio0: gpio@50000000 {
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compatible = "nordic,nrf-gpio";
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gpio-controller;
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reg = <0x50000000 0x200
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0x50000500 0x300>;
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#gpio-cells = <2>;
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label = "GPIO_0";
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status = "disabled";
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};
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i2c0: i2c@40003000 {
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compatible = "nordic,nrf-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003000 0x1000>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <3 1>;
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status = "disabled";
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label = "I2C_0";
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};
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pwm0: pwm@4001c000 {
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compatible = "nordic,nrf-pwm";
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reg = <0x4001c000 0x1000>;
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interrupts = <28 1>;
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status = "disabled";
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label = "PWM_0";
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};
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qdec: qdec@40012000 {
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compatible = "nordic,nrf-qdec";
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reg = <0x40012000 0x1000>;
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interrupts = <18 1>;
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status = "disabled";
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label = "QDEC";
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};
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spi0: spi@40004000 {
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compatible = "nordic,nrf-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40004000 0x1000>;
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interrupts = <4 1>;
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status = "disabled";
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label = "SPI_0";
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};
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rtc0: rtc@4000b000 {
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compatible = "nordic,nrf-rtc";
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reg = <0x4000b000 0x1000>;
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interrupts = <11 1>;
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status = "ok";
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label = "RTC_0";
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};
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rtc1: rtc@40011000 {
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compatible = "nordic,nrf-rtc";
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reg = <0x40011000 0x1000>;
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interrupts = <17 1>;
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status = "ok";
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label = "RTC_1";
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};
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timer0: timer@40008000 {
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compatible = "nordic,nrf-timer";
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status = "ok";
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reg = <0x40008000 0x1000>;
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interrupts = <8 1>;
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label = "TIMER_0";
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};
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timer1: timer@40009000 {
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compatible = "nordic,nrf-timer";
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status = "ok";
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reg = <0x40009000 0x1000>;
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interrupts = <9 1>;
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label = "TIMER_1";
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};
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timer2: timer@4000a000 {
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compatible = "nordic,nrf-timer";
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status = "ok";
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reg = <0x4000a000 0x1000>;
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interrupts = <10 1>;
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label = "TIMER_2";
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};
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temp: temp@4000c000 {
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compatible = "nordic,nrf-temp";
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reg = <0x4000c000 0x1000>;
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interrupts = <12 1>;
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status = "ok";
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label = "TEMP_0";
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};
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wdt: watchdog@40010000 {
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compatible = "nordic,nrf-watchdog";
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reg = <0x40010000 0x1000>;
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interrupts = <16 1>;
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status = "ok";
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label = "WDT";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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&sw_pwm {
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timer-instance = <2>;
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channel-count = <3>;
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clock-prescaler = <0>;
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ppi-base = <14>;
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gpiote-base = <0>;
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};
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