Raffael Rostagno 588c2e66e9 soc: esp32c6: Fix sleep routine ... PMU related functions need to be located in IRAM when sleep process is triggered, as cache is disabled past a certain point in the execution of the sleep process. Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>		2025-05-30 16:34:48 +02:00
..
common	soc: espressif: Filter LP Core from esptool command	2025-04-11 13:34:17 +02:00
esp32	soc: esp32: include ksched.h in esp32-mp.c	2025-05-06 20:36:26 +02:00
esp32c2	soc: espressif: update restart procedure	2025-04-05 11:02:13 +02:00
esp32c3	soc: espressif: update restart procedure	2025-04-05 11:02:13 +02:00
esp32c6	soc: esp32c6: Fix sleep routine	2025-05-30 16:34:48 +02:00
esp32s2	soc: espressif: update restart procedure	2025-04-05 11:02:13 +02:00
esp32s3	soc: espressif: update restart procedure	2025-04-05 11:02:13 +02:00
CMakeLists.txt
Kconfig	soc: espressif: esp32c6: Add LP Core	2025-03-21 17:05:20 +01:00
Kconfig.defconfig
Kconfig.soc
Kconfig.sysbuild	soc: espressif: Default MCUboot mode for ESP32 family	2024-09-16 20:17:44 +02:00
Kconfig.ulp	boards: espressif: esp32c6: Add LP Core board support	2025-03-21 17:05:20 +01:00
soc.yml	boards: espressif: esp32c6: Add LP Core board support	2025-03-21 17:05:20 +01:00