8564875a98
BSP builds for Nios II generate a linker.h and system.h which reflects the configuration for that CPU. This can vary depending on how the CPU is wired up in QSYS, so it needs to be at the SOC level--we essentially treat any given CPU configuration as a SOC in Zephyr build terms. Include these files from <arch/cpu.h>. Change-Id: I12f76600107fec1a14a2f9cb82b0f55915ec03a6 Origin: Altera Quartus tools, machine generated Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
107 lines
3 KiB
C
107 lines
3 KiB
C
/*
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* linker.h - Linker script mapping information
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*
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* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
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* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
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*
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* Generated: Tue May 03 11:35:27 MYT 2016
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*/
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/*
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* DO NOT MODIFY THIS FILE
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*
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* Changing this file will have subtle consequences
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* which will almost certainly lead to a nonfunctioning
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* system. If you do modify this file, be aware that your
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* changes will be overwritten and lost when this file
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* is generated again.
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*
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* DO NOT MODIFY THIS FILE
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*/
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/*
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* License Agreement
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*
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* Copyright (c) 2008
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* Altera Corporation, San Jose, California, USA.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* This agreement shall be governed in all respects by the laws of the State
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* of California and by the laws of the United States of America.
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*/
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#ifndef __LINKER_H_
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#define __LINKER_H_
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/*
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* BSP controls alt_load() behavior in crt0.
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*
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*/
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#define ALT_LOAD_EXPLICITLY_CONTROLLED
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/*
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* Base address and span (size in bytes) of each linker region
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*
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*/
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#define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20
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#define ONCHIP_FLASH_0_DATA_REGION_SPAN 753632
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#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000
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#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_SPAN 32
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#define ONCHIP_MEMORY2_0_REGION_BASE 0x400020
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#define ONCHIP_MEMORY2_0_REGION_SPAN 180192
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#define RESET_REGION_BASE 0x0
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#define RESET_REGION_SPAN 32
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/*
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* Devices associated with code sections
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*
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*/
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#define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY2_0
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#define ALT_RESET_DEVICE ONCHIP_FLASH_0_DATA
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#define ALT_RODATA_DEVICE ONCHIP_MEMORY2_0
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#define ALT_RWDATA_DEVICE ONCHIP_MEMORY2_0
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#define ALT_TEXT_DEVICE ONCHIP_FLASH_0_DATA
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/*
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* Initialization code at the reset address is allowed (e.g. no external bootloader).
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*
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*/
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#define ALT_ALLOW_CODE_AT_RESET
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/*
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* The alt_load() facility is called from crt0 to copy sections into RAM.
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*
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*/
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#define ALT_LOAD_COPY_EXCEPTIONS
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#define ALT_LOAD_COPY_RODATA
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#define ALT_LOAD_COPY_RWDATA
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#endif /* __LINKER_H_ */
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