83fe349ad5
Add ELC nodes to RA SoC DTS files and provide device-specific ELC signal enums for Devicetree bindings Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
389 lines
7.8 KiB
Text
389 lines
7.8 KiB
Text
/*
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* Copyright (c) 2024-2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <zephyr/dt-bindings/pwm/ra_pwm.h>
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#include <zephyr/dt-bindings/misc/renesas/ra-elc/ra6m3-elc.h>
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/ {
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soc {
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sram0: memory@1ffe0000 {
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compatible = "mmio-sram";
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reg = <0x1ffe0000 DT_SIZE_K(640)>;
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};
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ioport8: gpio@40040100 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040100 0x20>;
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port = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport9: gpio@40040120 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040120 0x20>;
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port = <9>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioporta: gpio@40040140 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040140 0x20>;
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port = <10>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioportb: gpio@40040160 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040160 0x20>;
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port = <11>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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sci5: sci5@400700a0 {
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compatible = "renesas,ra-sci";
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interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x400700a0 0x20>;
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clocks = <&pclka MSTPB 26>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <5>;
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status = "disabled";
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};
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};
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sci6: sci6@400700c0 {
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compatible = "renesas,ra-sci";
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interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x400700c0 0x20>;
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clocks = <&pclka MSTPB 25>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <6>;
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status = "disabled";
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};
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};
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sci7: sci7@400700e0 {
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compatible = "renesas,ra-sci";
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interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x400700e0 0x20>;
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clocks = <&pclka MSTPB 24>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <7>;
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status = "disabled";
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};
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};
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iic2: iic2@40053200 {
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compatible = "renesas,ra-iic";
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channel = <2>;
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reg = <0x40053200 0x100>;
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status = "disabled";
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};
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usbhs: usbhs@40060000 {
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compatible = "renesas,ra-usbhs";
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reg = <0x40060000 0x2000>;
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interrupts = <54 12>;
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interrupt-names = "usbhs-ir";
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num-bidir-endpoints = <10>;
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phys = <&usbhs_phy>;
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phys-clock = <&uclk>;
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status = "disabled";
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udc {
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compatible = "renesas,ra-udc";
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status = "disabled";
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};
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};
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adc@4005c000 {
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channel-available-mask = <0x1f00ff>;
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};
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adc@4005c200 {
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channel-available-mask = <0xf00ef>;
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};
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pwm13: pwm13@40078d00 {
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compatible = "renesas,ra-pwm";
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divider = <RA_PWM_SOURCE_DIV_1>;
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channel = <RA_PWM_CHANNEL_13>;
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clocks = <&pclkd MSTPD 6>;
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reg = <0x40078d00 0x100>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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};
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clocks: clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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xtal: clock-main-osc {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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clocks = <&xtal>;
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div = <2>;
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mul = <20 0>;
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status = "disabled";
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};
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pclkblock: pclkblock@4001e01c {
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compatible = "renesas,ra-cgc-pclk-block";
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reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
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<0x40047008 4>;
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reg-names = "MSTPA", "MSTPB","MSTPC",
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"MSTPD";
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#clock-cells = <0>;
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clocks = <&pll>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <120000000>;
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra-cgc-pclk";
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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div = <4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra-cgc-pclk";
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div = <4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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};
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bclk: bclk {
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compatible = "renesas,ra-cgc-pclk";
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div = <2>;
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bclkout: bclkout {
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compatible = "renesas,ra-cgc-busclk";
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clk-out-div = <2>;
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sdclk = <1>;
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#clock-cells = <0>;
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};
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#clock-cells = <2>;
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status = "okay";
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};
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uclk: uclk {
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compatible = "renesas,ra-cgc-pclk";
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div = <5>;
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra-cgc-pclk";
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div = <4>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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usbhs_phy: usbhs-phy {
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compatible = "renesas,ra-usbphyc";
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#phy-cells = <0>;
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};
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};
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&ioport0 {
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port-irqs = <&port_irq6 &port_irq7 &port_irq8
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&port_irq9 &port_irq10 &port_irq11
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&port_irq12 &port_irq13 &port_irq14>;
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port-irq-names = "port-irq6",
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"port-irq7",
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"port-irq8",
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"port-irq9",
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"port-irq10",
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"port-irq11",
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"port-irq12",
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"port-irq13",
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"port-irq14";
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port-irq6-pins = <0>;
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port-irq7-pins = <1>;
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port-irq8-pins = <2>;
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port-irq9-pins = <4>;
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port-irq10-pins = <5>;
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port-irq11-pins = <6>;
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port-irq12-pins = <8>;
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port-irq13-pins = <9 15>;
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port-irq14-pins = <10>;
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};
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&ioport1 {
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port-irqs = <&port_irq0 &port_irq1 &port_irq2
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&port_irq3 &port_irq4>;
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port-irq-names = "port-irq0",
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"port-irq1",
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"port-irq2",
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"port-irq3",
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"port-irq4";
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port-irq0-pins = <5>;
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port-irq1-pins = <1 4>;
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port-irq2-pins = <0>;
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port-irq3-pins = <10>;
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port-irq4-pins = <11>;
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};
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&ioport2 {
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port-irqs = <&port_irq0 &port_irq1 &port_irq2
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&port_irq3>;
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port-irq-names = "port-irq0",
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"port-irq1",
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"port-irq2",
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"port-irq3";
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port-irq0-pins = <6>;
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port-irq1-pins = <5>;
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port-irq2-pins = <3 13>;
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port-irq3-pins = <2 12>;
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};
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&ioport3 {
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port-irqs = <&port_irq5 &port_irq6
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&port_irq8 &port_irq9>;
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port-irq-names = "port-irq5",
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"port-irq6",
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"port-irq8",
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"port-irq9";
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port-irq5-pins = <2>;
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port-irq6-pins = <1>;
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port-irq8-pins = <5>;
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port-irq9-pins = <4>;
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};
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&ioport4 {
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port-irqs = <&port_irq0 &port_irq4 &port_irq5
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&port_irq6 &port_irq7 &port_irq8
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&port_irq9>;
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port-irq-names = "port-irq0",
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"port-irq4",
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"port-irq5",
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"port-irq6",
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"port-irq7",
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"port-irq8",
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"port-irq9";
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port-irq0-pins = <0>;
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port-irq4-pins = <2 11>;
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port-irq5-pins = <1 10>;
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port-irq6-pins = <9>;
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port-irq7-pins = <8>;
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port-irq8-pins = <15>;
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port-irq9-pins = <14>;
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};
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&ioport5 {
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port-irqs = <&port_irq11 &port_irq12 &port_irq14
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&port_irq15>;
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port-irq-names = "port-irq11",
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"port-irq12",
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"port-irq14",
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"port-irq15";
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port-irq11-pins = <1>;
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port-irq12-pins = <2>;
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port-irq14-pins = <5 12>;
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port-irq15-pins = <6 11>;
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};
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&ioport7 {
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port-irqs = <&port_irq7 &port_irq8 &port_irq10
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&port_irq11>;
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port-irq-names = "port-irq7",
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"port-irq8",
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"port-irq10",
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"port-irq11";
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port-irq7-pins = <6>;
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port-irq8-pins = <7>;
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port-irq10-pins = <9>;
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port-irq11-pins = <8>;
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};
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&dac_global {
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has-output-amplifier;
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};
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