cd83e85edc
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
113 lines
3.7 KiB
C
113 lines
3.7 KiB
C
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <kernel_structs.h>
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#include <wait_q.h>
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#include <string.h>
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#if defined(CONFIG_THREAD_MONITOR)
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/*
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* Add a thread to the kernel's list of active threads.
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*/
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static ALWAYS_INLINE void thread_monitor_init(struct k_thread *thread)
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{
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unsigned int key;
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key = irq_lock();
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thread->next_thread = _kernel.threads;
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_kernel.threads = thread;
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irq_unlock(key);
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}
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#else
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#define thread_monitor_init(thread) \
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do {/* do nothing */ \
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} while ((0))
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#endif /* CONFIG_THREAD_MONITOR */
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void _thread_entry_wrapper(_thread_entry_t thread,
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void *arg1,
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void *arg2,
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void *arg3);
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void _new_thread(char *stack_memory, size_t stack_size,
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_thread_entry_t thread_func,
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void *arg1, void *arg2, void *arg3,
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int priority, unsigned options)
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{
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_ASSERT_VALID_PRIO(priority, thread_func);
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struct k_thread *thread;
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struct __esf *stack_init;
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#ifdef CONFIG_INIT_STACKS
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memset(stack_memory, 0xaa, stack_size);
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#endif
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/* Initial stack frame for thread */
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stack_init = (struct __esf *)
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STACK_ROUND_DOWN(stack_memory +
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stack_size - sizeof(struct __esf));
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/* Setup the initial stack frame */
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stack_init->a0 = (uint32_t)thread_func;
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stack_init->a1 = (uint32_t)arg1;
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stack_init->a2 = (uint32_t)arg2;
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stack_init->a3 = (uint32_t)arg3;
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/*
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* Following the RISC-V architecture,
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* the MSTATUS register (used to globally enable/disable interrupt),
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* as well as the MEPC register (used to by the core to save the
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* value of the program counter at which an interrupt/exception occcurs)
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* need to be saved on the stack, upon an interrupt/exception
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* and restored prior to returning from the interrupt/exception.
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* This shall allow to handle nested interrupts.
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*
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* Given that context switching is performed via a system call exception
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* within the RISCV32 architecture implementation, initially set:
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* 1) MSTATUS to SOC_MSTATUS_DEF_RESTORE in the thread stack to enable
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* interrupts when the newly created thread will be scheduled;
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* 2) MEPC to the address of the _thread_entry_wrapper in the thread
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* stack.
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* Hence, when going out of an interrupt/exception/context-switch,
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* after scheduling the newly created thread:
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* 1) interrupts will be enabled, as the MSTATUS register will be
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* restored following the MSTATUS value set within the thread stack;
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* 2) the core will jump to _thread_entry_wrapper, as the program
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* counter will be restored following the MEPC value set within the
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* thread stack.
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*/
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stack_init->mstatus = SOC_MSTATUS_DEF_RESTORE;
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stack_init->mepc = (uint32_t)_thread_entry_wrapper;
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/* Initialize various struct k_thread members */
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thread = (struct k_thread *)stack_memory;
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_init_thread_base(&thread->base, priority, K_PRESTART, options);
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/* static threads overwrite it afterwards with real value */
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thread->init_data = NULL;
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thread->fn_abort = NULL;
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#ifdef CONFIG_THREAD_CUSTOM_DATA
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/* Initialize custom data field (value is opaque to kernel) */
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thread->custom_data = NULL;
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#endif
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thread->callee_saved.sp = (uint32_t)stack_init;
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thread_monitor_init(thread);
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}
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