zephyr/arch/riscv/core
Stephanos Ioannidis 7751fbca44 arch: riscv: Align semihost_exec function at 16-byte boundary
QEMU requires that the semihosting trap instruction sequence, which
consists of three uncompressed instructions, lie in the same page, and
refuses to interpret the trap sequence if these instructions are placed
across two different pages.

This commit adds 16-byte alignment requirement to the `semihost_exec`
function, which occupies 12 bytes, to ensure that the three trap
sequence instructions in this function are never placed across two
different pages.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-08-08 10:52:34 +02:00
..
offsets riscv: stop preserving the tp register needlessly 2022-06-23 13:12:05 -04:00
asm_macros.inc riscv: abstract RV32E register access 2022-06-23 13:12:05 -04:00
CMakeLists.txt riscv: pmp: switch over to the new implementation 2022-04-29 15:30:00 +02:00
coredump.c riscv: Introduce support for RV32E 2022-06-08 18:50:22 +09:00
cpu_idle.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
fatal.c riscv: stop preserving the tp register needlessly 2022-06-23 13:12:05 -04:00
irq_manage.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
irq_offload.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
isr.S soc: riscv: remove usage of SOC_ERET 2022-08-04 13:44:48 +02:00
pmp.c riscv: pmp: properly initialize per-thread m-mode/u-mode entry array 2022-06-23 15:56:00 -05:00
pmp.S asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
prep_c.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
reboot.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
reset.S asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
semihost.c arch: riscv: Align semihost_exec function at 16-byte boundary 2022-08-08 10:52:34 +02:00
smp.c riscv: new TLS-based arch_is_user_context() implementation 2022-06-23 13:12:05 -04:00
switch.S riscv: stop preserving the tp register needlessly 2022-06-23 13:12:05 -04:00
thread.c riscv: new TLS-based arch_is_user_context() implementation 2022-06-23 13:12:05 -04:00
tls.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
userspace.S asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00