804f164432
The STM32L433 has the same layout than the STM32L432, additionally it has GPIOD, GPIOE, I2C2, USART3 and SPI2. Also move USART3 and SPI2 out of stm32l4.dtsi since STM32L432 does not have it. Fixes #10909. Signed-off-by: Markus Roppelt <markus.roppelt@gmx.de>
140 lines
3.1 KiB
Text
140 lines
3.1 KiB
Text
/*
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* Copyright (c) 2018 Pushpal Sidhu
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/l4/stm32l4.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(640)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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erase-block-size = <4096>;
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};
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};
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pinctrl: pin-controller@48000000 {
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gpiod: gpio@48000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
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label = "GPIOD";
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};
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gpioe: gpio@48001000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
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label = "GPIOE";
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};
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gpiof: gpio@48001400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
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label = "GPIOF";
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};
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gpiog: gpio@48001800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
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label = "GPIOG";
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};
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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interrupts = <52 0>;
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status = "disabled";
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label = "UART_4";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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interrupts = <53 0>;
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status = "disabled";
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label = "UART_5";
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};
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i2c4: i2c@40008400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40008400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
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interrupts = <83 0>, <84 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_4";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 5>;
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status = "disabled";
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label = "SPI_2";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003c00 0x400>;
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interrupts = <51 5>;
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status = "disabled";
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label = "SPI_3";
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};
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otgfs_phy: otgfs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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label = "OTGFS_PHY";
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};
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usbotg_fs: otgfs@50000000 {
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compatible = "st,stm32-otgfs";
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reg = <0x50000000 0x40000>;
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interrupts = <67 0>;
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interrupt-names = "otgfs";
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num-bidir-endpoints = <6>;
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ram-size = <1280>;
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maximum-speed = "full-speed";
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phys = <&otgfs_phy>;
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status = "disabled";
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label= "OTGFS";
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};
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};
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};
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