7fdb525754
Same deal as in commit 4638652214 ("Kconfig: Use 'default' instead of
'def_bool' in Kconfig.defconfig files"), fixing new stuff that got
introduced since then.
Some symbols, like ALTERA_AVALON_PIO, are only defined in
Kconfig.defconfig files, and so need the def_bool.
Motivation (from the note at the end of
guides/kconfig/index.html#common-shorthands):
For a symbol defined in multiple locations (e.g., in a Kconfig.defconfig
file in Zephyr), it is best to only give the symbol type for the "base"
definition of the symbol, and to use 'default' (instead of 'def_<type>'
value) for the remaining definitions. That way, if the base definition
of the symbol is removed, the symbol ends up without a type, which
generates a warning that points to the other definitions. That makes the
extra definitions easier to discover and remove.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
188 lines
3.6 KiB
Text
188 lines
3.6 KiB
Text
# Kconfig.defconfig: RV32M1 SoC RISC-V core default configuration values
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#
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# Copyright (c) 2018 Foundries.io Ltd
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#
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# SPDX-License-Identifier: Apache-2.0
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if SOC_OPENISA_RV32M1_RISCV32
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config SOC
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string
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default "openisa_rv32m1"
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# 32 from event unit + 32 * (1 + max enabled INTMUX channel)
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config NUM_IRQS
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int
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default 288 if RV32M1_INTMUX_CHANNEL_7
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default 256 if RV32M1_INTMUX_CHANNEL_6
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default 224 if RV32M1_INTMUX_CHANNEL_5
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default 192 if RV32M1_INTMUX_CHANNEL_4
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default 160 if RV32M1_INTMUX_CHANNEL_3
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default 128 if RV32M1_INTMUX_CHANNEL_2
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default 96 if RV32M1_INTMUX_CHANNEL_1
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default 64 if RV32M1_INTMUX_CHANNEL_0
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default 32
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config XIP
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bool
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default y
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config RISCV_GENERIC_TOOLCHAIN
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bool
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default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr"
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default n
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config RISCV_SOC_CONTEXT_SAVE
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bool
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default y if SOC_OPENISA_RV32M1_RI5CY
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config RISCV_SOC_INTERRUPT_INIT
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bool
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default y
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# We need to disable the watchdog out of reset, as it's enabled by
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# default. Use the WDOG_INIT hook for doing that.
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config WDOG_INIT
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def_bool y
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# Built-in flash allocated to each chip. This configuration
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# assumes the Arm cores are disabled, as these base addresses
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# contain the Arm core vector tables if they are used.
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config RISCV32_RV32M1_ROM_BASE_ADDR
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hex
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default 0x00000000 if SOC_OPENISA_RV32M1_RI5CY
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default 0x01000000 if SOC_OPENISA_RV32M1_ZERO_RISCY
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config RISCV32_RV32M1_ROM_SIZE
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hex
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default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
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default 0x0003FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY
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config RISCV32_RV32M1_RAM_BASE_ADDR
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hex
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default 0x20000000 if SOC_OPENISA_RV32M1_RI5CY
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default 0x09000000 if SOC_OPENISA_RV32M1_ZERO_RISCY
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config RISCV32_RV32M1_RAM_SIZE
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hex
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default 0x00030000 if SOC_OPENISA_RV32M1_RI5CY
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default 0x00020000 if SOC_OPENISA_RV32M1_ZERO_RISCY
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# The event unit looks for vector tables at the end of each core's
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# flash space. These vector tables are not relocatable.
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config RISCV32_RV32M1_VECTOR_BASE_ADDR
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hex
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default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
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default 0x0103FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY
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config RISCV32_RV32M1_VECTOR_SIZE
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hex
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default 0x100
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 8000000 if SOC_OPENISA_RV32M1_RI5CY # SIRC at 8MHz
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if MULTI_LEVEL_INTERRUPTS
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config MAX_IRQ_PER_AGGREGATOR
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int
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default 32
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config 2ND_LEVEL_INTERRUPTS
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default y
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config 2ND_LVL_ISR_TBL_OFFSET
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int
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default 32
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config NUM_2ND_LEVEL_AGGREGATORS
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int
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default 8 if RV32M1_INTMUX_CHANNEL_7
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default 7 if RV32M1_INTMUX_CHANNEL_6
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default 6 if RV32M1_INTMUX_CHANNEL_5
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default 5 if RV32M1_INTMUX_CHANNEL_4
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default 4 if RV32M1_INTMUX_CHANNEL_3
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default 3 if RV32M1_INTMUX_CHANNEL_2
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default 2 if RV32M1_INTMUX_CHANNEL_1
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default 1 # just channel 0
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config 2ND_LVL_INTR_00_OFFSET
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int
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default 24
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config 2ND_LVL_INTR_01_OFFSET
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int
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default 25
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config 2ND_LVL_INTR_02_OFFSET
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int
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default 26
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config 2ND_LVL_INTR_03_OFFSET
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int
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default 27
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config 2ND_LVL_INTR_04_OFFSET
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int
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default 28
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config 2ND_LVL_INTR_05_OFFSET
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int
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default 29
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config 2ND_LVL_INTR_06_OFFSET
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int
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default 30
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config 2ND_LVL_INTR_07_OFFSET
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int
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default 31
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config RV32M1_INTMUX
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default y
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config RV32M1_INTMUX_CHANNEL_0
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default y
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config RV32M1_INTMUX_CHANNEL_1
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default y
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config RV32M1_INTMUX_CHANNEL_2
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default y
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config RV32M1_INTMUX_CHANNEL_3
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default y
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config RV32M1_INTMUX_CHANNEL_4
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default y
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config RV32M1_INTMUX_CHANNEL_5
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default y
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config RV32M1_INTMUX_CHANNEL_6
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default y
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config RV32M1_INTMUX_CHANNEL_7
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default y
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endif # MULTI_LEVEL_INTERRUPTS
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config PINMUX_RV32M1
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default y
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if GPIO
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config GPIO_RV32M1
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default y
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endif # GPIO
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if SERIAL
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config UART_RV32M1_LPUART
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def_bool y
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endif # SERIAL
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endif # SOC_OPENISA_RV32M1_RISCV32
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