Add build time optional PINCTRL support to common PWM driver for Microchip XEC MEC15xx and MEC172x families. Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
242 lines
4.1 KiB
Text
242 lines
4.1 KiB
Text
/*
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* Copyright (c) 2021, Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <microchip/mec172xnsz.dtsi>
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#include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>
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/ {
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model = "Microchip MEC172XEVB_ASSY6906 evaluation board";
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compatible = "microchip,mec172xevb_assy6906", "microchip,mec172xnsz";
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart1;
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};
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aliases {
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led0 = &led4;
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led1 = &led3;
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i2c0 = &i2c_smb_0;
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i2c-0 = &i2c_smb_0;
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i2c1 = &i2c_smb_1;
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i2c7 = &i2c_smb_2;
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};
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leds {
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compatible = "gpio-leds";
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led4: led_0 {
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/* GPIO241/CMP_VOUT0/PWM0_ALT on schematic,
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* LED4 on silkscreen.
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*/
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gpios = <&gpio_240_276 1 GPIO_ACTIVE_HIGH>;
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label = "LED 4";
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};
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led3: led_1 {
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/* GPIO175/CMP_VOUT1/PWM8_ALT on schematic,
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* LED5 on silkscreen.
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*/
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gpios = <&gpio_140_176 29 GPIO_ACTIVE_HIGH>;
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label = "LED 5";
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};
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};
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};
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&cpu0 {
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clock-frequency = <96000000>;
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status = "okay";
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};
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/* Initialize ECIA. Does not initialize child devices */
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&ecia {
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status = "okay";
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};
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/* Enable aggregated GIRQ24 and GIRQ25 for eSPI virtual wires interrupts */
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&girq24 {
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status = "okay";
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};
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&girq25 {
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status = "okay";
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};
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&rtimer {
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status = "okay";
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};
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&pcr {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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current-speed = <115200>;
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pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
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pinctrl-names = "default";
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};
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&adc0 {
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status = "okay";
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pinctrl-0 = <&adc00_gpio200 &adc03_gpio203
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&adc04_gpio204 &adc05_gpio205>;
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pinctrl-names = "default";
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};
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&espi0 {
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status = "okay";
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pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066
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&espi_alert_n_gpio063 &espi_clk_gpio065
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&espi_io0_gpio070 &espi_io1_gpio071
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&espi_io2_gpio072 &espi_io3_gpio073 >;
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pinctrl-names = "default";
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};
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/* enable various eSPI child devices (host facing) */
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&kbc0 {
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status = "okay";
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};
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&acpi_ec0 {
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status = "okay";
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};
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&acpi_ec1 {
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status = "okay";
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};
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&emi0 {
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status = "okay";
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};
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&p80bd0 {
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status = "okay";
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};
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/* I2C */
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&i2c_smb_0 {
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status = "okay";
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label = "I2C0";
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port_sel = <0>;
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pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;
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pinctrl-names = "default";
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pca9555@26 {
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compatible = "nxp,pca95xx";
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label = "GPIO_P0";
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/* Depends on JP53 for device address.
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* Pin 1-2 = A0, pin 3-4 = A1, pin 5-6 = A2.
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* Address is: 0100<A2><A1><A0>b.
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*
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* Default has pin 1-2 on JP53 connected,
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* resulting in device address 0x26.
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*/
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reg = <0x26>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&i2c00_scl_gpio004 {
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drive-open-drain;
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output-high;
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};
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&i2c00_sda_gpio003 {
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drive-open-drain;
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output-high;
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};
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&i2c_smb_1 {
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status = "okay";
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label = "I2C1";
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port_sel = <1>;
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pinctrl-0 = <&i2c01_scl_gpio131 &i2c01_sda_gpio130>;
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pinctrl-names = "default";
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};
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&i2c01_scl_gpio131 {
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drive-open-drain;
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output-high;
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};
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&i2c01_sda_gpio130 {
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drive-open-drain;
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output-high;
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};
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&i2c_smb_2 {
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status = "okay";
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label = "I2C7";
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port_sel = <7>;
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pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>;
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pinctrl-names = "default";
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};
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&i2c07_scl_gpio013 {
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drive-open-drain;
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output-high;
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};
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&i2c07_sda_gpio012 {
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drive-open-drain;
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output-high;
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};
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&spi0 {
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status = "okay";
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clock-frequency = <4000000>;
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lines = <4>;
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chip-select = <0>;
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port-sel = <0>; /* Shared SPI */
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pinctrl-0 = < &shd_cs0_n_gpio055
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&shd_clk_gpio056
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&shd_io0_gpio223
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&shd_io1_gpio224
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&shd_io2_gpio227
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&shd_io3_gpio016 >;
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pinctrl-names = "default";
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};
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&kscan0 {
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status = "okay";
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pinctrl-0 = < &ksi0_gpio017
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&ksi1_gpio020
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&ksi2_gpio021
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&ksi3_gpio026
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&ksi4_gpio027
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&ksi5_gpio030
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&ksi6_gpio031
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&ksi7_gpio032
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&kso00_gpio040
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&kso01_gpio045
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&kso02_gpio046
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&kso03_gpio047
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&kso04_gpio107
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&kso05_gpio112
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&kso06_gpio113
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&kso07_gpio120
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&kso08_gpio121
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&kso09_gpio122
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&kso10_gpio123
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&kso11_gpio124
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&kso12_gpio125
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&kso13_gpio126 >;
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pinctrl-names = "default";
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};
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&pwm0 {
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status = "okay";
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pinctrl-0 = <&pwm0_gpio053>;
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pinctrl-names = "default";
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};
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