7c12e86e06
Correct "zephyr,sram" property under /chosen node to make board and samples compatible with new SoC memory description. Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
107 lines
1.7 KiB
Text
107 lines
1.7 KiB
Text
/*
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* Copyright 2022 Google LLC
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* Copyright 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <espressif/esp32c3/esp32c3_fx4.dtsi>
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#include "esp32c3_042_oled-pinctrl.dtsi"
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#include <espressif/partitions_0x0_default.dtsi>
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/ {
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model = "01space ESP32C3 0.42 OLED";
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chosen {
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zephyr,sram = &sram1;
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zephyr,console = &usb_serial;
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zephyr,shell-uart = &usb_serial;
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zephyr,flash = &flash0;
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zephyr,code-partition = &slot0_partition;
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zephyr,canbus = &twai;
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zephyr,bt-hci = &esp32_bt_hci;
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zephyr,display = &eastrising_72x40;
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};
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aliases {
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i2c-0 = &i2c0;
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watchdog0 = &wdt0;
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};
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/* WS2812B LED connected to GPIO2 */
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};
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/* Have to use uart1 as some tests are hardcoded for that DTS node :/ */
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&uart1 {
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status = "okay";
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current-speed = <115200>;
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pinctrl-0 = <&uart1_default>;
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pinctrl-names = "default";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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pinctrl-0 = <&i2c0_default>;
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pinctrl-names = "default";
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eastrising_72x40: ssd1306@3c {
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compatible = "solomon,ssd1306fb";
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reg = <0x3c>;
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width = <72>;
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height = <40>;
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segment-offset = <28>;
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page-offset = <0>;
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display-offset = <0>;
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multiplex-ratio = <0x27>;
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prechargep = <0x22>;
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ready-time-ms = <10>;
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segment-remap;
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com-invdir;
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use-internal-iref;
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};
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};
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&spi2 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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pinctrl-0 = <&spim2_default>;
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pinctrl-names = "default";
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};
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&usb_serial {
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status = "okay";
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};
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&trng0 {
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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&wdt0 {
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status = "okay";
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};
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&timer0 {
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status = "okay";
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};
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&timer1 {
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status = "okay";
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};
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&wifi {
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status = "okay";
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};
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&esp32_bt_hci {
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status = "okay";
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};
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