7a55bda7e1
The idea here is to compute the PMP register set on demand i.e. upon scheduling in the affected threads, and only if changes occurred. A simple sequence number is used to stay in sync with the latest update. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
127 lines
3.5 KiB
C
127 lines
3.5 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Per-arch thread definition
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*
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* This file contains definitions for
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*
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* struct _thread_arch
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* struct _callee_saved
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*
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* necessary to instantiate instances of struct k_thread.
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_THREAD_H_
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#define ZEPHYR_INCLUDE_ARCH_RISCV_THREAD_H_
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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#if !defined(RV_FP_TYPE) && defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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#define RV_FP_TYPE uint64_t
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#else
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#define RV_FP_TYPE uint32_t
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#endif
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#endif
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#ifdef CONFIG_RISCV_PMP
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#ifdef CONFIG_64BIT
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#define RISCV_PMP_CFG_NUM (CONFIG_PMP_SLOT >> 3)
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#else
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#define RISCV_PMP_CFG_NUM (CONFIG_PMP_SLOT >> 2)
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#endif
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#endif
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#ifdef CONFIG_PMP_STACK_GUARD
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/*
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* PMP entries:
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* (1 for interrupt stack guard: None)
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* 4 for stacks guard: None
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* 1 for RAM: RW
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* 1 for other address space: RWX
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*/
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#define PMP_REGION_NUM_FOR_STACK_GUARD 6
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#define PMP_CFG_CSR_NUM_FOR_STACK_GUARD 2
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#endif /* CONFIG_PMP_STACK_GUARD */
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/*
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* The following structure defines the list of registers that need to be
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* saved/restored when a context switch occurs.
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*/
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struct _callee_saved {
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ulong_t sp; /* Stack pointer, (x2 register) */
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ulong_t ra; /* return address */
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ulong_t tp; /* thread pointer */
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ulong_t s0; /* saved register/frame pointer */
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ulong_t s1; /* saved register */
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ulong_t s2; /* saved register */
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ulong_t s3; /* saved register */
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ulong_t s4; /* saved register */
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ulong_t s5; /* saved register */
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ulong_t s6; /* saved register */
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ulong_t s7; /* saved register */
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ulong_t s8; /* saved register */
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ulong_t s9; /* saved register */
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ulong_t s10; /* saved register */
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ulong_t s11; /* saved register */
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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uint32_t fcsr; /* Control and status register */
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RV_FP_TYPE fs0; /* saved floating-point register */
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RV_FP_TYPE fs1; /* saved floating-point register */
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RV_FP_TYPE fs2; /* saved floating-point register */
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RV_FP_TYPE fs3; /* saved floating-point register */
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RV_FP_TYPE fs4; /* saved floating-point register */
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RV_FP_TYPE fs5; /* saved floating-point register */
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RV_FP_TYPE fs6; /* saved floating-point register */
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RV_FP_TYPE fs7; /* saved floating-point register */
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RV_FP_TYPE fs8; /* saved floating-point register */
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RV_FP_TYPE fs9; /* saved floating-point register */
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RV_FP_TYPE fs10; /* saved floating-point register */
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RV_FP_TYPE fs11; /* saved floating-point register */
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#endif
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};
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typedef struct _callee_saved _callee_saved_t;
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#define PMP_M_MODE_SLOTS 8 /* 8 is plenty enough for m-mode */
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struct _thread_arch {
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#ifdef CONFIG_USERSPACE
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ulong_t u_mode_pmpaddr_regs[CONFIG_PMP_SLOT];
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ulong_t u_mode_pmpcfg_regs[CONFIG_PMP_SLOT / sizeof(ulong_t)];
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unsigned int u_mode_pmp_domain_offset;
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unsigned int u_mode_pmp_end_index;
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unsigned int u_mode_pmp_update_nr;
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#endif
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#ifdef CONFIG_PMP_STACK_GUARD
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unsigned int m_mode_pmp_end_index;
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ulong_t m_mode_pmpaddr_regs[PMP_M_MODE_SLOTS];
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ulong_t m_mode_pmpcfg_regs[PMP_M_MODE_SLOTS / sizeof(ulong_t)];
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#endif
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/* legacy stuff below */
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#ifdef CONFIG_PMP_STACK_GUARD
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ulong_t s_pmpcfg[PMP_CFG_CSR_NUM_FOR_STACK_GUARD];
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ulong_t s_pmpaddr[PMP_REGION_NUM_FOR_STACK_GUARD];
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#endif
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#ifdef CONFIG_USERSPACE
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ulong_t priv_stack_start;
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ulong_t u_pmpcfg[RISCV_PMP_CFG_NUM];
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ulong_t u_pmpaddr[CONFIG_PMP_SLOT];
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#endif
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};
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typedef struct _thread_arch _thread_arch_t;
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_THREAD_H_ */
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