7a06df9cc3
Add support for ITE it51xxx SoC. NOTE: it51526aw is not support RISCV_ISA_EXT_C. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
119 lines
3 KiB
C
119 lines
3 KiB
C
/*
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* Copyright (c) 2025 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc_common.h>
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#include <zephyr/kernel.h>
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static mm_reg_t ecpm_base = DT_REG_ADDR(DT_NODELABEL(ecpm));
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/* it51xxx ECPM registers definition */
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/* 0x03: PLL Control */
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#define ECPM_PLLCTRL 0x03
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void chip_pll_ctrl(enum chip_pll_mode mode)
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{
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volatile uint8_t _pll_ctrl __unused;
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sys_write8(mode, ecpm_base + ECPM_PLLCTRL);
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/*
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* for deep doze / sleep mode
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* This load operation will ensure PLL setting is taken into
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* control register before wait for interrupt instruction.
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*/
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_pll_ctrl = sys_read8(ecpm_base + ECPM_PLLCTRL);
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}
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#ifdef CONFIG_SOC_IT51XXX_CPU_IDLE_GATING
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/* Preventing CPU going into idle mode during command queue. */
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static atomic_t cpu_idle_disabled;
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void chip_permit_idle(void)
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{
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atomic_dec(&cpu_idle_disabled);
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}
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void chip_block_idle(void)
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{
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atomic_inc(&cpu_idle_disabled);
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}
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bool cpu_idle_not_allowed(void)
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{
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return atomic_get(&cpu_idle_disabled);
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}
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#endif
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/* The routine must be called with interrupts locked */
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void riscv_idle(enum chip_pll_mode mode, unsigned int key)
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{
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/*
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* The routine is called with interrupts locked (in kernel/idle()).
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* But on kernel/context test_kernel_cpu_idle test, the routine will be
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* called without interrupts locked. Hence we disable M-mode external
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* interrupt here to protect the below content.
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*/
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csr_clear(mie, MIP_MEIP);
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sys_trace_idle();
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/* Chip doze after wfi instruction */
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chip_pll_ctrl(mode);
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/* Wait for interrupt */
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__asm__ volatile("wfi");
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/*
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* Enable M-mode external interrupt
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* An interrupt can not be fired yet until we enable global interrupt
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*/
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csr_set(mie, MIP_MEIP);
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/* Restore global interrupt lockout state */
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irq_unlock(key);
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}
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void arch_cpu_idle(void)
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{
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#ifdef CONFIG_SOC_IT51XXX_CPU_IDLE_GATING
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/*
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* The EC processor(CPU) cannot be in the k_cpu_idle() during
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* the transactions with the CQ mode(DMA mode). Otherwise,
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* the EC processor would be clock gated.
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*/
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if (cpu_idle_not_allowed()) {
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/* Restore global interrupt lockout state */
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irq_unlock(MSTATUS_IEN);
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} else {
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#endif
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riscv_idle(CHIP_PLL_DOZE, MSTATUS_IEN);
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#ifdef CONFIG_SOC_IT51XXX_CPU_IDLE_GATING
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}
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#endif
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}
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void arch_cpu_atomic_idle(unsigned int key)
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{
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riscv_idle(CHIP_PLL_DOZE, key);
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}
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void soc_prep_hook(void)
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{
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struct gpio_ite_ec_regs *const gpio_regs = GPIO_ITE_EC_REGS_BASE;
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struct gctrl_ite_ec_regs *const gctrl_regs = GCTRL_ITE_EC_REGS_BASE;
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/* Scratch ROM0 is 4kb size */
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gctrl_regs->GCTRL_SCR0SZR = IT51XXX_GCTRL_SCRSIZE_4K;
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/* bit4: wake up CPU if it is in low power mode and an interrupt is pending. */
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gctrl_regs->GCTRL_SPCTRL9 |= IT51XXX_GCTRL_ALTIE;
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/* UART1 and UART2 board init */
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/* bit3: UART1 and UART2 belong to the EC side. */
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gctrl_regs->GCTRL_RSTDMMC |= IT51XXX_GCTRL_UART1SD | IT51XXX_GCTRL_UART2SD;
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/* Reset UART before config it */
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gctrl_regs->GCTRL_RSTC4 = IT51XXX_GCTRL_RUART;
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/* Switch UART1 and UART2 on without hardware flow control */
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gpio_regs->GPIO_GCR1 |=
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IT51XXX_GPIO_U1CTRL_SIN0_SOUT0_EN | IT51XXX_GPIO_U2CTRL_SIN1_SOUT1_EN;
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}
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