a5fd0d184a
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
161 lines
4.8 KiB
C
161 lines
4.8 KiB
C
/*
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* Copyright (c) 2020 IoT.bzh <julien.massot@iot.bzh>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <soc.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
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#include <zephyr/irq.h>
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#define DT_DRV_COMPAT renesas_rcar_cmt
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#define TIMER_IRQ DT_INST_IRQN(0)
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#define TIMER_BASE_ADDR DT_INST_REG_ADDR(0)
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#define TIMER_CLOCK_FREQUENCY DT_INST_PROP(0, clock_frequency)
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#define CLOCK_SUBSYS DT_INST_CLOCKS_CELL(0, module)
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#define CYCLES_PER_SEC TIMER_CLOCK_FREQUENCY
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#define CYCLES_PER_TICK (CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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#if defined(CONFIG_TEST)
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const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_INST(0, renesas_rcar_cmt));
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#endif
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static struct rcar_cpg_clk mod_clk = {
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.module = DT_INST_CLOCKS_CELL(0, module),
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.domain = DT_INST_CLOCKS_CELL(0, domain),
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};
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BUILD_ASSERT(CYCLES_PER_TICK > 1,
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"CYCLES_PER_TICK must be greater than 1");
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#define CMCOR0_OFFSET 0x018 /* constant register 0 */
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#define CMCNT0_OFFSET 0x014 /* counter 0 */
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#define CMCSR0_OFFSET 0x010 /* control/status register 0 */
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#define CMCOR1_OFFSET 0x118 /* constant register 1 */
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#define CMCNT1_OFFSET 0x114 /* counter 1 */
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#define CMCSR1_OFFSET 0x110 /* control/status register 1 */
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#define CMCLKE 0xB00 /* CLK enable register */
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#define CLKEN0 BIT(5) /* Enable Clock for channel 0 */
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#define CLKEN1 BIT(6) /* Enable Clock for channel 1 */
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#define CMSTR0_OFFSET 0x000 /* Timer start register 0 */
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#define CMSTR1_OFFSET 0x100 /* Timer start register 1 */
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#define START_BIT BIT(0)
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#define CSR_CLK_DIV_1 0x00000007
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#define CSR_ENABLE_COUNTER_IN_DEBUG BIT(3)
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#define CSR_ENABLE_INTERRUPT BIT(5)
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#define CSR_FREE_RUN BIT(8)
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#define CSR_WRITE_FLAG BIT(13)
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#define CSR_OVERFLOW_FLAG BIT(14)
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#define CSR_MATCH_FLAG BIT(15)
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static void cmt_isr(void *arg)
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{
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ARG_UNUSED(arg);
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uint32_t reg_val;
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/* clear the interrupt */
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reg_val = sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET);
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reg_val &= ~CSR_MATCH_FLAG;
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sys_write32(reg_val, TIMER_BASE_ADDR + CMCSR0_OFFSET);
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/* Announce to the kernel */
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sys_clock_announce(1);
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}
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uint32_t sys_clock_elapsed(void)
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{
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/* Always return 0 for tickful operation */
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return 0;
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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return sys_read32(TIMER_BASE_ADDR + CMCNT1_OFFSET);
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}
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/*
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* Initialize both channels at same frequency,
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* Set the first one to generates interrupt at CYCLES_PER_TICK.
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* The second one is used for cycles count, the match value is set
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* at max uint32_t.
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*/
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static int sys_clock_driver_init(void)
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{
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const struct device *clk;
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uint32_t reg_val;
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int i, ret;
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clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
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if (!device_is_ready(clk)) {
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return -ENODEV;
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}
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ret = clock_control_on(clk, (clock_control_subsys_t)&mod_clk);
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if (ret < 0) {
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return ret;
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}
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/* Supply clock for both channels */
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sys_write32(CLKEN0 | CLKEN1, TIMER_BASE_ADDR + CMCLKE);
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/* Stop both channels */
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reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR0_OFFSET);
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reg_val &= ~START_BIT;
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sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR0_OFFSET);
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reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR1_OFFSET);
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reg_val &= ~START_BIT;
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sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR1_OFFSET);
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/* Set the timers as 32-bit, with RCLK/1 clock */
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sys_write32(CSR_FREE_RUN | CSR_CLK_DIV_1 | CSR_ENABLE_INTERRUPT,
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TIMER_BASE_ADDR + CMCSR0_OFFSET);
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/* Do not enable interrupts for the second channel */
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sys_write32(CSR_FREE_RUN | CSR_CLK_DIV_1,
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TIMER_BASE_ADDR + CMCSR1_OFFSET);
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/* Set the first channel match to CYCLES Per tick*/
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sys_write32(CYCLES_PER_TICK, TIMER_BASE_ADDR + CMCOR0_OFFSET);
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/* Set the second channel match to max uint32 */
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sys_write32(0xffffffff, TIMER_BASE_ADDR + CMCOR1_OFFSET);
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/* Reset the counter for first channel, check WRFLG first */
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while (sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET) & CSR_WRITE_FLAG) {
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;
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}
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sys_write32(0, TIMER_BASE_ADDR + CMCNT0_OFFSET);
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for (i = 0; i < 1000; i++) {
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if (!sys_read32(TIMER_BASE_ADDR + CMCNT0_OFFSET)) {
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break;
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}
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}
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__ASSERT(sys_read32(TIMER_BASE_ADDR + CMCNT0_OFFSET) == 0,
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"Fail to clear CMCNT0 register");
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/* Connect timer interrupt for channel 0*/
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IRQ_CONNECT(TIMER_IRQ, 0, cmt_isr, 0, 0);
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irq_enable(TIMER_IRQ);
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/* Start the timers */
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sys_write32(START_BIT, TIMER_BASE_ADDR + CMSTR0_OFFSET);
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sys_write32(START_BIT, TIMER_BASE_ADDR + CMSTR1_OFFSET);
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return 0;
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}
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
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CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
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