73c63f9ca6
Add initial support for Renesas RZ/V2N Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com> Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
21 lines
374 B
C
21 lines
374 B
C
/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Renesas RZ/V2N Group
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*/
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#include <zephyr/init.h>
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#include <bsp_api.h>
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/* System core clock is set to 200 MHz after reset */
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uint32_t SystemCoreClock = 200000000;
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void soc_early_init_hook(void)
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{
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bsp_clock_init();
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}
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