zephyr/soc/xtensa/intel_adsp/cavs_v18
Guennadi Liakhovetski 7242b567fc cavs: fix LSPGISTS and LSPGCTL access
On cAVS 1.8, 2.0 and 2.5 LSPGISTS and LSPGCTL are located in a
different shim register range, they cannot be accessed, using the
usual SHIM_BASE offset.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2021-01-11 16:10:23 -05:00
..
include cavs: fix LSPGISTS and LSPGCTL access 2021-01-11 16:10:23 -05:00
Kconfig.defconfig.series intel_adsp: disable IPM_INTEL_ADSP 2021-01-06 07:53:46 -06:00
Kconfig.series soc/xtensa/intel_adsp: Upstream updates 2020-10-21 06:38:53 -04:00
Kconfig.soc soc/xtensa/intel_adsp: Upstream updates 2020-10-21 06:38:53 -04:00
linker.ld rimage: update rimage: add configuration and extended manifest 2021-01-11 16:10:23 -05:00