6ff5ac05e4
Implementation of pinmux of usdhc depends on board design. Usdhc driver could change pinmux according to SD mode, SoC should provide API for this. Board pinmux should register its pinmux function to SoC. Signed-off-by: Jun Yang <jun.yang@nxp.com>
280 lines
6.7 KiB
C
280 lines
6.7 KiB
C
/*
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* Copyright (c) 2017,2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <linker/sections.h>
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#include <fsl_clock.h>
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#include <arch/cpu.h>
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#include <cortex_m/exc.h>
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#include <fsl_flexspi_nor_boot.h>
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#if CONFIG_USB_DC_NXP_EHCI
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#include "usb_phy.h"
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#include "usb_dc_mcux.h"
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#endif
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#ifdef CONFIG_INIT_ARM_PLL
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/* ARM PLL configuration for RUN mode */
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const clock_arm_pll_config_t armPllConfig = {
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.loopDivider = 100U
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};
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#endif
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#ifdef CONFIG_INIT_SYS_PLL
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/* SYS PLL configuration for RUN mode */
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const clock_sys_pll_config_t sysPllConfig = {
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.loopDivider = 1U
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};
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#endif
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#ifdef CONFIG_INIT_USB1_PLL
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/* USB1 PLL configuration for RUN mode */
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const clock_usb_pll_config_t usb1PllConfig = {
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.loopDivider = 0U
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};
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#endif
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#if CONFIG_USB_DC_NXP_EHCI
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/* USB PHY condfiguration */
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#define BOARD_USB_PHY_D_CAL (0x0CU)
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#define BOARD_USB_PHY_TXCAL45DP (0x06U)
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#define BOARD_USB_PHY_TXCAL45DM (0x06U)
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#endif
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#ifdef CONFIG_INIT_ENET_PLL
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/* ENET PLL configuration for RUN mode */
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const clock_enet_pll_config_t ethPllConfig = {
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#if defined(CONFIG_SOC_MIMXRT1021) || defined(CONFIG_SOC_MIMXRT1015)
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.enableClkOutput500M = true,
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#endif
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#ifdef CONFIG_ETH_MCUX
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.enableClkOutput = true,
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#endif
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.enableClkOutput25M = false,
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.loopDivider = 1,
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};
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#endif
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#if CONFIG_USB_DC_NXP_EHCI
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usb_phy_config_struct_t usbPhyConfig = {
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BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
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};
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#endif
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#ifdef CONFIG_INIT_VIDEO_PLL
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const clock_video_pll_config_t videoPllConfig = {
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.loopDivider = 31,
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.postDivider = 8,
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.numerator = 0,
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.denominator = 0,
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};
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#endif
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#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
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const __imx_boot_data_section BOOT_DATA_T boot_data = {
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.start = CONFIG_FLASH_BASE_ADDRESS,
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.size = CONFIG_FLASH_SIZE,
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.plugin = PLUGIN_FLAG,
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.placeholder = 0xFFFFFFFF,
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};
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const __imx_boot_ivt_section ivt image_vector_table = {
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.hdr = IVT_HEADER,
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.entry = CONFIG_FLASH_BASE_ADDRESS + CONFIG_TEXT_SECTION_OFFSET,
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.reserved1 = IVT_RSVD,
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#ifdef CONFIG_DEVICE_CONFIGURATION_DATA
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.dcd = (uint32_t) dcd_data,
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#else
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.dcd = (uint32_t) NULL,
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#endif
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.boot_data = (uint32_t) &boot_data,
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.self = (uint32_t) &image_vector_table,
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.csf = (uint32_t)CSF_ADDRESS,
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.reserved2 = IVT_RSVD,
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};
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#endif
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/**
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*
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* @brief Initialize the system clock
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*
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* @return N/A
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*
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*/
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static ALWAYS_INLINE void clkInit(void)
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{
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/* Boot ROM did initialize the XTAL, here we only sets external XTAL
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* OSC freq
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*/
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CLOCK_SetXtalFreq(24000000U);
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CLOCK_SetRtcXtalFreq(32768U);
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/* Set PERIPH_CLK2 MUX to OSC */
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CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1);
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/* Set PERIPH_CLK MUX to PERIPH_CLK2 */
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CLOCK_SetMux(kCLOCK_PeriphMux, 0x1);
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/* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz
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*/
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DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
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/* Waiting for DCDC_STS_DC_OK bit is asserted */
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while (DCDC_REG0_STS_DC_OK_MASK !=
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(DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
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;
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}
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#ifdef CONFIG_INIT_ARM_PLL
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CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
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#endif
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#ifdef CONFIG_INIT_SYS_PLL
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CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */
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#endif
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#ifdef CONFIG_INIT_USB1_PLL
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CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
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#endif
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#ifdef CONFIG_INIT_ENET_PLL
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CLOCK_InitEnetPll(ðPllConfig);
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#endif
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#ifdef CONFIG_INIT_VIDEO_PLL
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CLOCK_InitVideoPll(&videoPllConfig);
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#endif
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CLOCK_SetDiv(kCLOCK_ArmDiv, CONFIG_ARM_DIV); /* Set ARM PODF */
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CLOCK_SetDiv(kCLOCK_AhbDiv, CONFIG_AHB_DIV); /* Set AHB PODF */
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CLOCK_SetDiv(kCLOCK_IpgDiv, CONFIG_IPG_DIV); /* Set IPG PODF */
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/* Set PRE_PERIPH_CLK to PLL1, 1200M */
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CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3);
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/* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
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CLOCK_SetMux(kCLOCK_PeriphMux, 0x0);
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#ifdef CONFIG_UART_MCUX_LPUART
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/* Configure UART divider to default */
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CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
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CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
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#endif
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#ifdef CONFIG_I2C_MCUX_LPI2C
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CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); /* Set I2C source as USB1 PLL 480M */
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CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); /* Set I2C divider to 6 */
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#endif
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#ifdef CONFIG_SPI_MCUX_LPSPI
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CLOCK_SetMux(kCLOCK_LpspiMux, 1); /* Set SPI source to USB1 PFD0 720M */
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CLOCK_SetDiv(kCLOCK_LpspiDiv, 7); /* Set SPI divider to 8 */
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#endif
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#ifdef CONFIG_DISPLAY_MCUX_ELCDIF
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CLOCK_SetMux(kCLOCK_LcdifPreMux, 2);
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CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4);
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CLOCK_SetDiv(kCLOCK_LcdifDiv, 1);
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#endif
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#if CONFIG_USB_DC_NXP_EHCI
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CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M,
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig);
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#endif
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/* Keep the system clock running so SYSTICK can wake up the system from
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* wfi.
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*/
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CLOCK_SetMode(kCLOCK_ModeRun);
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}
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#if defined(CONFIG_DISK_ACCESS_USDHC1) || \
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defined(CONFIG_DISK_ACCESS_USDHC2)
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/* Usdhc driver needs to re-configure pinmux
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* Pinmux depends on board design.
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* From the perspective of Usdhc driver,
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* it can't access board specific function.
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* So SoC provides this for board to register
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* its usdhc pinmux and for usdhc to access
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* pinmux.
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*/
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static usdhc_pin_cfg_cb g_usdhc_pin_cfg_cb;
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void imxrt_usdhc_pinmux_cb_register(usdhc_pin_cfg_cb cb)
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{
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g_usdhc_pin_cfg_cb = cb;
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}
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void imxrt_usdhc_pinmux(u16_t nusdhc, bool init,
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u32_t speed, u32_t strength)
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{
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if (g_usdhc_pin_cfg_cb)
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g_usdhc_pin_cfg_cb(nusdhc, init,
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speed, strength);
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}
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#endif
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/**
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*
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* @brief Perform basic hardware initialization
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*
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* Initialize the interrupt controller device drivers.
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* Also initialize the timer device driver, if required.
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*
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* @return 0
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*/
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static int imxrt_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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unsigned int oldLevel; /* old interrupt lock level */
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/* disable interrupts */
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oldLevel = irq_lock();
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/* Watchdog disable */
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if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0) {
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WDOG1->WCR &= ~WDOG_WCR_WDE_MASK;
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}
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if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0) {
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WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
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}
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RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
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RTWDOG->TOVAL = 0xFFFF;
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RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK)
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| RTWDOG_CS_UPDATE_MASK;
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/* Disable Systick which might be enabled by bootrom */
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if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0) {
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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}
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SCB_EnableICache();
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if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
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SCB_EnableDCache();
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}
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/* Initialize system clock */
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clkInit();
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/*
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* install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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/* restore interrupt state */
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irq_unlock(oldLevel);
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return 0;
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}
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SYS_INIT(imxrt_init, PRE_KERNEL_1, 0);
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