6e8775ff84
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an undesirable API for the following reasons: - it's inconsistent with the rest of the DT_NODE_HAS_FOO names - DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand for macros which are equivalent to DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) && - DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck - DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway - it is seen as a somewhat aesthetically challenged name Replace all users with DT_NODE_HAS_STATUS(..., okay), which is semantically equivalent. This is mostly done with sed, but a few remaining cases were done by hand, along with whitespace, docs, and comment changes. These special cases include the Nordic SOC static assert files. Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
78 lines
2.2 KiB
C
78 lines
2.2 KiB
C
/*
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* Copyright (c) 2019, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <fsl_iomuxc.h>
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#include <fsl_gpio.h>
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static int mimxrt1010_evk_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_11_GPIOMUX_IO11,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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IOMUXC_GPR->GPR26 &= ~(IOMUXC_GPR_GPR26_GPIO_SEL(1 << 11));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_05_GPIO2_IO05,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay)
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/* LPUART1 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_09_LPUART1_RXD,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_10_LPUART1_TXD,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay)
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/* LPI2C1 SCL, SDA */
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IOMUXC_SetPinMux(IOMUXC_GPIO_01_LPI2C1_SDA, 1);
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IOMUXC_SetPinMux(IOMUXC_GPIO_02_LPI2C1_SCL, 1);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_02_LPI2C1_SCL,
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IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_01_LPI2C1_SDA,
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IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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return 0;
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}
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SYS_INIT(mimxrt1010_evk_init, PRE_KERNEL_1, 0);
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