6e272b14bd
stm32f407 SoC is an extension of stm32f405 SoC with additional support of ethernet and DCMI. Hence, in dts description, this should be represented by stm32f407.dtsi including stm32f405.dtsi. The opposite was proposed today in stm32 .dtsi files. This commit fixes the inclusion model and renames stm32f407-pinctrl.dtsi into stm32f405-pinctrl.dtsi Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
38 lines
1,021 B
Text
38 lines
1,021 B
Text
/*
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* Copyright (c) 2017 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <dt-bindings/pinctrl/stm32-pinctrl.h>
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/ {
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soc {
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pinctrl: pin-controller {
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usart3_pins_a: usart3@0 {
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rx_tx {
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rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
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tx = <STM32_PIN_PB10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
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};
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};
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usart3_pins_b: usart3@1 {
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rx_tx {
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rx = <STM32_PIN_PD9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
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tx = <STM32_PIN_PD8 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
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};
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};
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usart6_pins_a: usart6@0 {
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rx_tx {
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rx = <STM32_PIN_PG14 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
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tx = <STM32_PIN_PG9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
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};
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};
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usart6_pins_b: usart6@1 {
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rx_tx {
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rx = <STM32_PIN_PC7 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
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tx = <STM32_PIN_PC6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
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};
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};
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};
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};
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};
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