6b3749d2ff
Add driver implementation and header files for a MEC172x aggregated interrupt driver. Enable the parent(ECIA) node to have the driver initialize interrupt hardware for use. Enable child nodes for those GIRQs used for aggregation. Refer to chip documention for the list of GIRQs restricted to aggregation and those which support direct mode. Add chip level device tree node for MEC172x EC interrupt aggregator parent and GIRQ children. Each child node contains a list of sources representing the source bit position in the GIRQ registers. Add DT bindings for ECIA and GIRQ nodes. Add build file(s) and configuration items for the MEC172x ECIA aggregated interrupt driver. Add and enable the MEC172x interrupt driver on the MEC172x evaluation board(EVB). Enable parent node to initialize ECIA hardware. Child nodes are left disabled until a future driver needs them. Signed-off-by: Scott Worley <scott.worley@microchip.com>
75 lines
2 KiB
Text
75 lines
2 KiB
Text
# interrupt controller configuration options
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# Copyright (c) 2015 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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menu "Interrupt Controllers"
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config ARCV2_INTERRUPT_UNIT
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bool "ARCv2 Interrupt Unit"
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default y
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depends on ARC
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help
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The ARCv2 interrupt unit has 16 allocated exceptions associated with
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vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
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The interrupt unit is optional in the ARCv2-based processors. When
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building a processor, you can configure the processor to include an
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interrupt unit. The ARCv2 interrupt unit is highly programmable.
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config PLIC
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bool "Platform Level Interrupt Controller (PLIC)"
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default y
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depends on SOC_FAMILY_RISCV_PRIVILEGE
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select RISCV_HAS_PLIC
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select MULTI_LEVEL_INTERRUPTS
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select 2ND_LEVEL_INTERRUPTS
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help
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Platform Level Interrupt Controller provides support
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for external interrupt lines defined by the RISC-V SoC;
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config SWERV_PIC
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bool "SweRV EH1 Programmable Interrupt Controller (PIC)"
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default n
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help
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Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU;
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config VEXRISCV_LITEX_IRQ
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bool "VexRiscv LiteX Interrupt controller"
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depends on SOC_RISCV32_LITEX_VEXRISCV
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help
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IRQ implementation for LiteX VexRiscv
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config LEON_IRQMP
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bool "GRLIB IRQMP interrupt controller"
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default y
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depends on SOC_SPARC_LEON
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help
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GRLIB IRQMP and IRQAMP
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source "drivers/interrupt_controller/Kconfig.multilevel"
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source "drivers/interrupt_controller/Kconfig.loapic"
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source "drivers/interrupt_controller/Kconfig.dw"
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source "drivers/interrupt_controller/Kconfig.it8xxx2"
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source "drivers/interrupt_controller/Kconfig.stm32"
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source "drivers/interrupt_controller/Kconfig.cavs"
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source "drivers/interrupt_controller/Kconfig.rv32m1"
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source "drivers/interrupt_controller/Kconfig.sam0"
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source "drivers/interrupt_controller/Kconfig.gic"
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source "drivers/interrupt_controller/Kconfig.npcx"
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source "drivers/interrupt_controller/Kconfig.intel_vtd"
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source "drivers/interrupt_controller/Kconfig.esp32"
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source "drivers/interrupt_controller/Kconfig.xec"
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endmenu
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