69b9d345ae
Kill of nvic.h and use either CMSIS helper functions for NVIC or direct NVIC register access via CMSIS for IRQ handling code. Jira: ZEP-1568 Change-Id: If21910b9293121efe85c3c9076a1c2b475ef91ef Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM CORTEX-M3 interrupt management
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*
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*
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* Interrupt management: enabling/disabling and dynamic ISR
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* connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for
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* connecting ISRs at runtime.
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <arch/arm/cortex_m/cmsis.h>
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#include <misc/__assert.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <sw_isr_table.h>
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#include <irq.h>
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extern void __reserved(void);
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#define NUM_IRQS_PER_REG 32
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#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
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#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
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/**
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*
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* @brief Enable an interrupt line
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*
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* Enable the interrupt. After this call, the CPU will receive interrupts for
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* the specified <irq>.
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*
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* @return N/A
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*/
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void _arch_irq_enable(unsigned int irq)
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{
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NVIC_EnableIRQ((IRQn_Type)irq);
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}
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/**
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*
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* @brief Disable an interrupt line
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*
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* Disable an interrupt line. After this call, the CPU will stop receiving
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* interrupts for the specified <irq>.
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*
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* @return N/A
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*/
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void _arch_irq_disable(unsigned int irq)
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{
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NVIC_DisableIRQ((IRQn_Type)irq);
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}
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/**
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* @brief Return IRQ enable state
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*
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* @param irq IRQ line
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* @return interrupt enable state, true or false
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*/
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int _arch_irq_is_enabled(unsigned int irq)
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{
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return NVIC->ISER[REG_FROM_IRQ(irq)] & (1 << BIT_FROM_IRQ(irq));
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}
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/**
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* @internal
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*
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* @brief Set an interrupt's priority
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*
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* The priority is verified if ASSERT_ON is enabled. The maximum number
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* of priority levels is a little complex, as there are some hardware
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* priority levels which are reserved: three for various types of exceptions,
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* and possibly one additional to support zero latency interrupts.
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*
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* @return N/A
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*/
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void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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/* Hardware priority levels 0 and 1 reserved for Kernel use.
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* So we add 2 to the requested priority level. If we support
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* ZLI, 2 is also reserved so we add 3.
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*/
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#if CONFIG_ZERO_LATENCY_IRQS
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/* If we have zero latency interrupts, that makes priority level 2
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* a case with special semantics; it is not masked by irq_lock().
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* Our policy is to express priority levels with special properties
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* via flags
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*/
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if (flags & IRQ_ZERO_LATENCY) {
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prio = 2;
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} else {
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prio += _IRQ_PRIO_OFFSET;
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}
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#else
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ARG_UNUSED(flags);
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prio += _IRQ_PRIO_OFFSET;
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#endif
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/* The last priority level is also used by PendSV exception, but
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* allow other interrupts to use the same level, even if it ends up
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* affecting performance (can still be useful on systems with a
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* reduced set of priorities, like Cortex-M0/M0+).
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*/
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__ASSERT(prio <= ((1 << CONFIG_NUM_IRQ_PRIO_BITS) - 1),
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"invalid priority %d! values must be less than %d\n",
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prio - _IRQ_PRIO_OFFSET,
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(1 << CONFIG_NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
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NVIC_SetPriority((IRQn_Type)irq, prio);
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}
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/**
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*
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* @brief Spurious interrupt handler
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*
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* Installed in all dynamic interrupt slots at boot time. Throws an error if
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* called.
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*
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* See __reserved().
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*
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* @return N/A
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*/
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void _irq_spurious(void *unused)
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{
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ARG_UNUSED(unused);
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__reserved();
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}
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