692fda47fc
We don't need to set up GDT data descriptors for setting %gs. Instead, we use the x86 MSRs to set GS_BASE and KERNEL_GS_BASE. We don't currently allow user mode to set %gs on its own, but later on if we do, we have everything set up to issue 'swapgs' instructions on syscall or IRQ. Unused entries in the GDT have been removed. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
117 lines
2.6 KiB
C
117 lines
2.6 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_THREAD_H_
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#define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_THREAD_H_
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#define X86_THREAD_FLAG_ALL 0x01 /* _thread_arch.flags: entire state saved */
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/*
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* GDT selectors - these must agree with the GDT layout in locore.S.
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*/
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#define X86_KERNEL_CS_32 0x08 /* 32-bit kernel code */
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#define X86_KERNEL_DS_32 0x10 /* 32-bit kernel data */
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#define X86_KERNEL_CS 0x18 /* 64-bit kernel code */
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#define X86_KERNEL_DS 0x20 /* 64-bit kernel data */
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#define X86_KERNEL_CPU0_TR 0x28 /* 64-bit task state segment */
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#define X86_KERNEL_CPU1_TR 0x38 /* 64-bit task state segment */
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#define X86_KERNEL_CPU2_TR 0x48 /* 64-bit task state segment */
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#define X86_KERNEL_CPU3_TR 0x58 /* 64-bit task state segment */
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/*
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* Some SSE definitions. Ideally these will ultimately be shared with 32-bit.
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*/
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#define X86_FXSAVE_SIZE 512 /* size and alignment of buffer ... */
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#define X86_FXSAVE_ALIGN 16 /* ... for FXSAVE/FXRSTOR ops */
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#define X86_MXCSR_SANE 0x1dc0 /* enable division-by-zero exception */
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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/*
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* 64-bit Task State Segment. One defined per CPU.
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*/
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struct x86_tss64 {
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/*
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* Architecturally-defined portion. It is somewhat tedious to
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* enumerate each member specifically (rather than using arrays)
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* but we need to get (some of) their offsets from assembly.
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*/
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u8_t reserved0[4];
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u64_t rsp0; /* privileged stacks */
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u64_t rsp1;
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u64_t rsp2;
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u8_t reserved[8];
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u64_t ist1; /* interrupt stacks */
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u64_t ist2;
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u64_t ist3;
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u64_t ist4;
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u64_t ist5;
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u64_t ist6;
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u64_t ist7;
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u8_t reserved1[10];
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u16_t iomapb; /* offset to I/O base */
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/*
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* Zephyr specific portion. Stash per-CPU data here for convenience.
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*/
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struct _cpu *cpu;
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} __packed __aligned(8);
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typedef struct x86_tss64 x86_tss64_t;
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/*
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* The _callee_saved registers are unconditionally saved/restored across
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* context switches; the _thread_arch registers are only preserved when
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* the thread is interrupted. _arch_thread.flags tells __resume when to
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* cheat and only restore the first set. For more details see locore.S.
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*/
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struct _callee_saved {
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u64_t rsp;
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u64_t rbx;
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u64_t rbp;
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u64_t r12;
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u64_t r13;
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u64_t r14;
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u64_t r15;
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u64_t rip;
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u64_t rflags;
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};
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typedef struct _callee_saved _callee_saved_t;
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struct _thread_arch {
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u8_t flags;
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u64_t rax;
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u64_t rcx;
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u64_t rdx;
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u64_t rsi;
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u64_t rdi;
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u64_t r8;
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u64_t r9;
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u64_t r10;
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u64_t r11;
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char __aligned(X86_FXSAVE_ALIGN) sse[X86_FXSAVE_SIZE];
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};
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typedef struct _thread_arch _thread_arch_t;
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_THREAD_H_ */
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