67a47445eb
Fix various bugs with the new IDC layer that show up in edge cases where code relies on correct timing of IPIs (unsurprisingly there is a lot of code that recovers anyway even if the IPI doesn't arrive promptly). Leaving this as a separate patch because the prior code in the PR has already been reviewed and it "mostly" worked: The unmasking of the L2 interrupt bit (remember there are three layers of masking of the IDC interrupt) was always operating on CPU0 at CPU startup because the code had been copied blindly. Unmask the CPU we're actually launching. It turns out cAVS 2.x re-masks this on CPU launch automatically. The global init code to unmask all these interrupts at startup had the same bug, even though it turned out to be needless (the initialization state has it unmasked until it turns it back off). Do it right anyway. Similarly add code to clear out existing interrupt latch state by ACKing all IDC interrupts at startup. Seems needless, but behavior isn't documented so let's be safe. Flag CPU0 as always "active" for the purposes of IPIs. Forgot to do this earlier, oops. Signed-off-by: Andy Ross <andrew.j.ross@intel.com> |
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| .. | ||
| esp32 | ||
| esp32s2 | ||
| intel_adsp | ||
| intel_s1000 | ||
| nxp_adsp | ||
| sample_controller | ||
| CMakeLists.txt | ||