88808f1247
Quark SE Lakemont core has a hardware bug where the LOAPIC does not properly notify the IOAPIC to clear the IRR bit for level- triggered interrupts. This patch introduces a workaround where the vector ID of the in-service interrupt is manually written to the IOAPIC_EOI register, resulting in the bit being cleared. Unfortunately, in the context where EOI happens it's very difficult to identify which IRQ line is being serviced, so this is done unconditionally for all interrupts vectors whether they are registered in the IOAPIC RTE table or not. Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
/* ioapic_priv.h - private IOAPIC APIs */
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/*
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* Copyright (c) 2012-2015 Wind River Systems, Inc.
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* Copyright (c) 2015 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __INCioapic_privh
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#define __INCioapic_privh
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/* IO APIC direct register offsets */
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#define IOAPIC_IND 0x00 /* Index Register */
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#define IOAPIC_DATA 0x10 /* IO window (data) - pc.h */
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#define IOAPIC_IRQPA 0x20 /* IRQ Pin Assertion Register */
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#define IOAPIC_EOI 0x40 /* EOI Register */
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/* IO APIC indirect register offset */
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#define IOAPIC_ID 0x00 /* IOAPIC ID */
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#define IOAPIC_VERS 0x01 /* IOAPIC Version */
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#define IOAPIC_ARB 0x02 /* IOAPIC Arbitration ID */
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#define IOAPIC_BOOT 0x03 /* IOAPIC Boot Configuration */
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#define IOAPIC_REDTBL 0x10 /* Redirection Table (24 * 64bit) */
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/* Interrupt delivery type */
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#define IOAPIC_DT_APIC 0x0 /* APIC serial bus */
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#define IOAPIC_DT_FS 0x1 /* Front side bus message*/
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/* Version register bits */
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#define IOAPIC_MRE_MASK 0x00ff0000 /* Max Red. entry mask */
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#define IOAPIC_PRQ 0x00008000 /* this has IRQ reg */
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#define IOAPIC_VERSION 0x000000ff /* version number */
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/* Redirection table entry number */
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#define MAX_REDTABLE_ENTRIES 24
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/* Redirection table entry bits: upper 32 bit */
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#define IOAPIC_DESTINATION 0xff000000
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/* Redirection table entry bits: lower 32 bit */
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#define IOAPIC_VEC_MASK 0x000000ff
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#endif
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