6531d1c649
ARMv8-A SoCs enter EL3 after reset. Add a new config option (CONFIG_SWITCH_TO_EL1) to switch from EL3 to EL1 at boot and default it to 'y'. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
145 lines
3.2 KiB
ArmAsm
145 lines
3.2 KiB
ArmAsm
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Reset handler
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*
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* Reset handler that prepares the system for running C code.
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include "vector_table.h"
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#include "macro.h"
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/**
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*
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* @brief Reset vector
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*
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* Ran when the system comes out of reset. The processor is in thread mode with
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* privileged level. At this point, neither SP_EL0 nor SP_ELx point to a valid
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* area in SRAM.
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*
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* When these steps are completed, jump to z_arm64_prep_c(), which will finish
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* setting up the system for running C code.
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*
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* @return N/A
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*/
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GTEXT(__reset)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset)
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/*
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* The entry point is located at the __reset symbol, which is fetched by a XIP
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* image playing the role of a bootloader, which jumps to it, not through the
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* reset vector mechanism. Such bootloaders might want to search for a __start
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* symbol instead, so create that alias here.
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*/
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GTEXT(__start)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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#ifdef CONFIG_SWITCH_TO_EL1
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switch_el x1, 3f, 2f, 1f
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3:
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/* Disable MMU and async exceptions routing to EL1 */
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msr sctlr_el1, xzr
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/* Disable EA/IRQ/FIQ routing to EL3 and set EL1 to AArch64 */
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mov x0, xzr
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orr x0, x0, #(SCR_EL3_RW)
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msr scr_el3, x0
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/* On eret return to EL1 with DAIF masked */
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mov x0, xzr
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orr x0, x0, #(DAIF_MASK)
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orr x0, x0, #(SPSR_EL3_TO_EL1)
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orr x0, x0, #(SPSR_EL3_h)
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msr spsr_el3, x0
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adr x0, 1f
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msr elr_el3, x0
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eret
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2:
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/* Boot from EL2 not supported */
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bl .
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1:
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#endif
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/* Setup vector table */
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adr x0, _vector_table
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switch_el x1, 3f, 2f, 1f
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3:
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/* Initialize VBAR */
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msr vbar_el3, x0
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/* SError, IRQ and FIQ routing enablement in EL3 */
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mrs x0, scr_el3
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orr x0, x0, #(SCR_EL3_IRQ | SCR_EL3_FIQ | SCR_EL3_EA)
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msr scr_el3, x0
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/* Disable access trapping in EL3 for NEON/FP */
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msr cptr_el3, xzr
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/*
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* Enable the instruction cache, stack pointer and data access
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* alignment checks and disable speculative loads.
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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b 0f
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2:
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/* Initialize VBAR */
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msr vbar_el2, x0
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/* SError, IRQ and FIQ routing enablement in EL2 */
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mrs x0, hcr_el2
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orr x0, x0, #(HCR_EL2_FMO | HCR_EL2_IMO | HCR_EL2_AMO)
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msr hcr_el2, x0
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/* Disable access trapping in EL2 for NEON/FP */
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msr cptr_el2, xzr
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/*
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* Enable the instruction cache, stack pointer and data access
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* alignment checks and disable speculative loads.
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el2
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orr x0, x0, x1
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msr sctlr_el2, x0
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b 0f
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1:
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/* Initialize VBAR */
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msr vbar_el1, x0
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/* Disable access trapping in EL1 for NEON/FP */
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mov x1, #(CPACR_EL1_FPEN_NOTRAP)
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msr cpacr_el1, x1
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/*
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* Enable the instruction cache, stack pointer and data access
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* alignment checks and disable speculative loads.
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el1
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orr x0, x0, x1
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msr sctlr_el1, x0
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0:
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isb
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/* Enable the SError interrupt */
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msr daifclr, #(DAIFSET_ABT)
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/* Switch to SP_ELn and setup the stack */
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msr spsel, #1
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ldr x0, =(_interrupt_stack)
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add x0, x0, #(CONFIG_ISR_STACK_SIZE)
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mov sp, x0
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bl z_arm64_prep_c
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