643661cb44
And remove the ad hoc prototype in cpu.c for Intel64. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
114 lines
3 KiB
C
114 lines
3 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <kernel_arch_data.h>
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#include <kernel_arch_func.h>
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#include <kernel_structs.h>
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#include <arch/x86/multiboot.h>
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#include <drivers/interrupt_controller/loapic.h>
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/*
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* Map of CPU logical IDs to CPU local APIC IDs. By default,
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* we assume this simple identity mapping, as found in QEMU.
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* The symbol is weak so that boards/SoC files can override.
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*/
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__weak u8_t x86_cpu_loapics[] = { 0, 1, 2, 3 };
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extern char x86_ap_start[]; /* AP entry point in locore.S */
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extern u8_t _exception_stack[];
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extern u8_t _exception_stack1[];
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extern u8_t _exception_stack2[];
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extern u8_t _exception_stack3[];
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Z_GENERIC_SECTION(.tss)
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struct x86_tss64 tss0 = {
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.ist1 = (u64_t) _interrupt_stack + CONFIG_ISR_STACK_SIZE,
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.ist7 = (u64_t) _exception_stack + CONFIG_EXCEPTION_STACK_SIZE,
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.iomapb = 0xFFFF,
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.cpu = &(_kernel.cpus[0])
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};
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#if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 1)
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Z_GENERIC_SECTION(.tss)
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struct x86_tss64 tss1 = {
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.ist1 = (u64_t) _interrupt_stack1 + CONFIG_ISR_STACK_SIZE,
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.ist7 = (u64_t) _exception_stack1 + CONFIG_EXCEPTION_STACK_SIZE,
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.iomapb = 0xFFFF,
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.cpu = &(_kernel.cpus[1])
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};
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#endif
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#if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 2)
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Z_GENERIC_SECTION(.tss)
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struct x86_tss64 tss2 = {
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.ist1 = (u64_t) _interrupt_stack2 + CONFIG_ISR_STACK_SIZE,
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.ist7 = (u64_t) _exception_stack2 + CONFIG_EXCEPTION_STACK_SIZE,
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.iomapb = 0xFFFF,
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.cpu = &(_kernel.cpus[2])
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};
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#endif
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#if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 3)
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Z_GENERIC_SECTION(.tss)
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struct x86_tss64 tss3 = {
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.ist1 = (u64_t) _interrupt_stack3 + CONFIG_ISR_STACK_SIZE,
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.ist7 = (u64_t) _exception_stack3 + CONFIG_EXCEPTION_STACK_SIZE,
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.iomapb = 0xFFFF,
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.cpu = &(_kernel.cpus[3])
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};
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#endif
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struct x86_cpuboot x86_cpuboot[] = {
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{
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.tr = X86_KERNEL_CPU0_TR,
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.gs = X86_KERNEL_CPU0_GS,
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.sp = (u64_t) _interrupt_stack + CONFIG_ISR_STACK_SIZE,
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.fn = z_x86_prep_c
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},
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#if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 1)
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{
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.tr = X86_KERNEL_CPU1_TR,
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.gs = X86_KERNEL_CPU1_GS,
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},
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#endif
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#if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 2)
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{
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.tr = X86_KERNEL_CPU2_TR,
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.gs = X86_KERNEL_CPU2_GS,
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},
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#endif
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#if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 3)
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{
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.tr = X86_KERNEL_CPU3_TR,
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.gs = X86_KERNEL_CPU3_GS,
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},
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#endif
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};
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/*
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* Send the INIT/STARTUP IPI sequence required to start up CPU 'cpu_num', which
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* will enter the kernel at fn(---, arg), running on the specified stack.
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*/
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void z_arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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void (*fn)(int key, void *data), void *arg)
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{
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u8_t vector = ((unsigned long) x86_ap_start) >> 12;
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u8_t apic_id = x86_cpu_loapics[cpu_num];
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x86_cpuboot[cpu_num].sp = (u64_t) Z_THREAD_STACK_BUFFER(stack) + sz;
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x86_cpuboot[cpu_num].fn = fn;
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x86_cpuboot[cpu_num].arg = arg;
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z_loapic_ipi(apic_id, LOAPIC_ICR_IPI_INIT, 0);
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k_busy_wait(10000);
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z_loapic_ipi(apic_id, LOAPIC_ICR_IPI_STARTUP, vector);
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while (x86_cpuboot[cpu_num].ready == 0) {
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}
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}
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