6399ad50f4
Add support for configuring UART/UARTE peripheral pins. Co-authored-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no> Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
130 lines
3 KiB
C
130 lines
3 KiB
C
/*
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* Copyright (c) 2021 Nordic Semiconductor ASA
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
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/*
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* The whole nRF pin configuration information is encoded in a 32-bit bitfield
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* organized as follows:
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*
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* - 31..16: Pin function.
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* - 15..13: Reserved.
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* - 12: Pin low power mode.
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* - 11..8: Pin output drive configuration.
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* - 7..6: Pin pull configuration.
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* - 5..0: Pin number (combination of port and pin).
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*/
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/**
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* @name nRF pin configuration bit field positions and masks.
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* @{
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*/
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/** Position of the function field. */
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#define NRF_FUN_POS 16U
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/** Mask for the function field. */
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#define NRF_FUN_MSK 0xFFFFU
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/** Position of the low power field. */
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#define NRF_LP_POS 12U
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/** Mask for the low power field. */
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#define NRF_LP_MSK 0x1U
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/** Position of the drive configuration field. */
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#define NRF_DRIVE_POS 8U
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/** Mask for the drive configuration field. */
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#define NRF_DRIVE_MSK 0xFU
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/** Position of the pull configuration field. */
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#define NRF_PULL_POS 6U
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/** Mask for the pull configuration field. */
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#define NRF_PULL_MSK 0x3U
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/** Position of the pin field. */
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#define NRF_PIN_POS 0U
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/** Mask for the pin field. */
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#define NRF_PIN_MSK 0x3FU
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/** @} */
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/**
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* @name nRF pinctrl pin functions.
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* @{
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*/
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/** UART TX */
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#define NRF_FUN_UART_TX 0U
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/** UART RX */
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#define NRF_FUN_UART_RX 1U
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/** UART RTS */
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#define NRF_FUN_UART_RTS 2U
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/** UART CTS */
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#define NRF_FUN_UART_CTS 3U
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/** @} */
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/**
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* @name nRF pinctrl output drive.
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* @note Values match nrf_gpio_pin_drive_t constants.
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* @{
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*/
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/** Standard '0', standard '1'. */
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#define NRF_DRIVE_S0S1 0U
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/** High drive '0', standard '1'. */
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#define NRF_DRIVE_H0S1 1U
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/** Standard '0', high drive '1'. */
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#define NRF_DRIVE_S0H1 2U
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/** High drive '0', high drive '1'. */
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#define NRF_DRIVE_H0H1 3U
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/** Disconnect '0' standard '1'. */
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#define NRF_DRIVE_D0S1 4U
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/** Disconnect '0', high drive '1'. */
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#define NRF_DRIVE_D0H1 5U
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/** Standard '0', disconnect '1'. */
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#define NRF_DRIVE_S0D1 6U
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/** High drive '0', disconnect '1'. */
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#define NRF_DRIVE_H0D1 7U
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/** Extra high drive '0', extra high drive '1'. */
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#define NRF_DRIVE_E0E1 11U
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/** @} */
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/**
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* @name nRF pinctrl pull-up/down.
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* @note Values match nrf_gpio_pin_pull_t constants.
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* @{
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*/
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/** Pull-up disabled. */
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#define NRF_PULL_NONE 0U
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/** Pull-down enabled. */
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#define NRF_PULL_DOWN 1U
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/** Pull-up enabled. */
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#define NRF_PULL_UP 3U
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/** @} */
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/**
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* @name nRF pinctrl low power mode.
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* @{
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*/
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/** Input. */
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#define NRF_LP_DISABLE 0U
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/** Output. */
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#define NRF_LP_ENABLE 1U
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/** @} */
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/**
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* @brief Utility macro to build nRF psels property entry.
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*
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* @param fun Pin function configuration (see NRF_FUNC_{name} macros).
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* @param port Port (0 or 1).
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* @param pin Pin (0..31).
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*/
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#define NRF_PSEL(fun, port, pin) \
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((((((port) * 32U) + (pin)) & NRF_PIN_MSK) << NRF_PIN_POS) | \
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((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ */
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