1cee7be552
RT11xx series has similar pin configuration peripheral to RT10xx, with some differences in register layout. Create new pinctrl definition header file, and reuse existing driver code for RT10xx. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
/*
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* Copyright (c) 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_mcux_rt_pinctrl
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#include <drivers/pinctrl.h>
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#include <soc.h>
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#include <fsl_iomuxc.h>
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#include <fsl_gpio.h>
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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/* configure all pins */
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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uint32_t mux_register = pins[i].pinmux.mux_register;
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uint32_t mux_mode = pins[i].pinmux.mux_mode;
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uint32_t input_register = pins[i].pinmux.input_register;
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uint32_t input_daisy = pins[i].pinmux.input_daisy;
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uint32_t config_register = pins[i].pinmux.config_register;
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uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
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volatile uint32_t *gpr_register =
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(volatile uint32_t *)pins[i].pinmux.gpr_register;
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if (gpr_register) {
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/* Set or clear specified GPR bit for this mux */
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if (pins[i].pinmux.gpr_val) {
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*gpr_register |=
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(pins[i].pinmux.gpr_val << pins[i].pinmux.gpr_shift);
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} else {
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*gpr_register &= ~(0x1 << pins[i].pinmux.gpr_shift);
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}
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}
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IOMUXC_SetPinMux(mux_register, mux_mode, input_register,
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input_daisy, config_register,
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MCUX_RT_INPUT_ENABLE(pin_ctrl_flags));
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if (config_register) {
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IOMUXC_SetPinConfig(mux_register, mux_mode, input_register,
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input_daisy, config_register,
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pin_ctrl_flags & (~(0x1 << MCUX_RT_INPUT_ENABLE_SHIFT)));
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}
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}
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return 0;
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}
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static int mcux_pinctrl_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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#ifdef CONFIG_SOC_SERIES_IMX_RT10XX
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CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
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CLOCK_EnableClock(kCLOCK_IomuxcGpr);
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#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
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CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr);
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#endif
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return 0;
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}
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SYS_INIT(mcux_pinctrl_init, PRE_KERNEL_1, 0);
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