603f068690
Previous rename from CONFIG_* to DT_* left a few remaining CONFIG_*. So rename them manually now. Fix #13753 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
81 lines
3.7 KiB
C
81 lines
3.7 KiB
C
/* SoC level DTS fixup file */
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/* CCM configuration */
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#define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS
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#define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10)
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#define DT_ICCM_BASE_ADDRESS DT_ARC_ICCM_0_BASE_ADDRESS
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#define DT_ICCM_SIZE (DT_ARC_ICCM_0_SIZE >> 10)
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/*
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* UART configuration
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*/
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#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_F0008000_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_F0008000_IRQ_0
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#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_F0008000_CLOCK_FREQUENCY
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#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_F0008000_CURRENT_SPEED
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#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_F0008000_LABEL
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#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_F0008000_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_F0009000_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_F0009000_IRQ_0
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#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_F0009000_CLOCK_FREQUENCY
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#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_F0009000_CURRENT_SPEED
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#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_F0009000_LABEL
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#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_F0009000_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_2_BASE_ADDR DT_NS16550_F000A000_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_2_IRQ DT_NS16550_F000A000_IRQ_0
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#define DT_UART_NS16550_PORT_2_CLK_FREQ DT_NS16550_F000A000_CLOCK_FREQUENCY
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#define DT_UART_NS16550_PORT_2_BAUD_RATE DT_NS16550_F000A000_CURRENT_SPEED
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#define DT_UART_NS16550_PORT_2_NAME DT_NS16550_F000A000_LABEL
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#define DT_UART_NS16550_PORT_2_IRQ_PRI DT_NS16550_F000A000_IRQ_0_PRIORITY
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/*
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* GPIO configuration
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*/
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#define DT_GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002000_BASE_ADDRESS
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#define DT_GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0002000_BITS
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#define CONFIG_GPIO_DW_0_NAME DT_SNPS_DESIGNWARE_GPIO_F0002000_LABEL
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#define DT_GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0
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#define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0_PRIORITY
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#define DT_GPIO_DW_0_IRQ_FLAGS 0
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#define DT_GPIO_DW_1_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F000200C_BASE_ADDRESS
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#define DT_GPIO_DW_1_BITS DT_SNPS_DESIGNWARE_GPIO_F000200C_BITS
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#define CONFIG_GPIO_DW_1_NAME DT_SNPS_DESIGNWARE_GPIO_F000200C_LABEL
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#define DT_GPIO_DW_1_IRQ DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0
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#define CONFIG_GPIO_DW_1_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0_PRIORITY
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#define DT_GPIO_DW_2_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002018_BASE_ADDRESS
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#define DT_GPIO_DW_2_BITS DT_SNPS_DESIGNWARE_GPIO_F0002018_BITS
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#define CONFIG_GPIO_DW_2_NAME DT_SNPS_DESIGNWARE_GPIO_F0002018_LABEL
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#define DT_GPIO_DW_2_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0
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#define CONFIG_GPIO_DW_2_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0_PRIORITY
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#define DT_GPIO_DW_3_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002024_BASE_ADDRESS
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#define DT_GPIO_DW_3_BITS DT_SNPS_DESIGNWARE_GPIO_F0002024_BITS
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#define CONFIG_GPIO_DW_3_NAME DT_SNPS_DESIGNWARE_GPIO_F0002024_LABEL
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#define DT_GPIO_DW_3_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0
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#define CONFIG_GPIO_DW_3_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0_PRIORITY
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/*
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* SPI configuration
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*/
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#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS
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#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_F0006000_LABEL
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#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0
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#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY
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#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS
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#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_F0007000_LABEL
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#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0
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#define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY
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#define DT_SPI_DW_IRQ_FLAGS 0
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#define DT_SPI_DW_SPI_CLOCK DT_NS16550_F0009000_CLOCK_FREQUENCY
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/* End of SoC Level DTS fixup file */
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