5a9ff03c21
Config struct is constant and attempting to modify it triggers a fault. Signed-off-by: Luis Ubieda <luisf@croxel.com>
602 lines
16 KiB
C
602 lines
16 KiB
C
/*
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* Copyright (c) 2020 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT adi_adxl345
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#include <zephyr/drivers/sensor.h>
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#include <zephyr/init.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/__assert.h>
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#include "adxl345.h"
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LOG_MODULE_REGISTER(ADXL345, CONFIG_SENSOR_LOG_LEVEL);
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#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
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static bool adxl345_bus_is_ready_i2c(const union adxl345_bus *bus)
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{
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return device_is_ready(bus->i2c.bus);
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}
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static int adxl345_reg_access_i2c(const struct device *dev, uint8_t cmd, uint8_t reg_addr,
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uint8_t *data, size_t length)
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{
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const struct adxl345_dev_config *cfg = dev->config;
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if (cmd == ADXL345_READ_CMD) {
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return i2c_burst_read_dt(&cfg->bus.i2c, reg_addr, data, length);
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} else {
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return i2c_burst_write_dt(&cfg->bus.i2c, reg_addr, data, length);
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}
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}
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#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
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#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
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static bool adxl345_bus_is_ready_spi(const union adxl345_bus *bus)
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{
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return spi_is_ready_dt(&bus->spi);
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}
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int adxl345_reg_access_spi(const struct device *dev, uint8_t cmd, uint8_t reg_addr,
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uint8_t *data, size_t length)
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{
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const struct adxl345_dev_config *cfg = dev->config;
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uint8_t access = reg_addr | cmd | (length == 1 ? 0 : ADXL345_MULTIBYTE_FLAG);
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const struct spi_buf buf[2] = {{.buf = &access, .len = 1}, {.buf = data, .len = length}};
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const struct spi_buf_set rx = {.buffers = buf, .count = ARRAY_SIZE(buf)};
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struct spi_buf_set tx = {
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.buffers = buf,
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.count = 2,
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};
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int ret;
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if (cmd == ADXL345_READ_CMD) {
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tx.count = 1;
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ret = spi_transceive_dt(&cfg->bus.spi, &tx, &rx);
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return ret;
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} else {
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ret = spi_write_dt(&cfg->bus.spi, &tx);
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return ret;
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}
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}
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#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
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int adxl345_reg_access(const struct device *dev, uint8_t cmd, uint8_t addr,
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uint8_t *data, size_t len)
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{
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const struct adxl345_dev_config *cfg = dev->config;
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return cfg->reg_access(dev, cmd, addr, data, len);
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}
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int adxl345_reg_write(const struct device *dev, uint8_t addr, uint8_t *data,
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uint8_t len)
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{
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return adxl345_reg_access(dev, ADXL345_WRITE_CMD, addr, data, len);
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}
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int adxl345_reg_read(const struct device *dev, uint8_t addr, uint8_t *data,
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uint8_t len)
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{
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return adxl345_reg_access(dev, ADXL345_READ_CMD, addr, data, len);
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}
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int adxl345_reg_write_byte(const struct device *dev, uint8_t addr, uint8_t val)
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{
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return adxl345_reg_write(dev, addr, &val, 1);
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}
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int adxl345_reg_read_byte(const struct device *dev, uint8_t addr, uint8_t *buf)
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{
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return adxl345_reg_read(dev, addr, buf, 1);
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}
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int adxl345_reg_write_mask(const struct device *dev,
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uint8_t reg_addr,
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uint8_t mask,
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uint8_t data)
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{
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int ret;
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uint8_t tmp;
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ret = adxl345_reg_read_byte(dev, reg_addr, &tmp);
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if (ret) {
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return ret;
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}
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tmp &= ~mask;
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tmp |= data;
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return adxl345_reg_write_byte(dev, reg_addr, tmp);
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}
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static inline bool adxl345_bus_is_ready(const struct device *dev)
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{
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const struct adxl345_dev_config *cfg = dev->config;
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return cfg->bus_is_ready(&cfg->bus);
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}
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int adxl345_get_status(const struct device *dev,
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uint8_t *status1,
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uint16_t *fifo_entries)
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{
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uint8_t buf[2], length = 1U;
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int ret;
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ret = adxl345_reg_read(dev, ADXL345_INT_SOURCE, buf, length);
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*status1 = buf[0];
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ret = adxl345_reg_read(dev, ADXL345_FIFO_STATUS_REG, buf+1, length);
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if (fifo_entries) {
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*fifo_entries = buf[1] & 0x3F;
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}
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return ret;
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}
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/**
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* Configure the operating parameters for the FIFO.
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* @param dev - The device structure.
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* @param mode - FIFO Mode. Specifies FIFO operating mode.
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* Accepted values: ADXL345_FIFO_BYPASSED
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* ADXL345_FIFO_STREAMED
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* ADXL345_FIFO_TRIGGERED
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* ADXL345_FIFO_OLD_SAVED
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* @param trigger - FIFO trigger. Links trigger event to appropriate INT.
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* Accepted values: ADXL345_INT1
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* ADXL345_INT2
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* @param fifo_samples - FIFO Samples. Watermark number of FIFO samples that
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* triggers a FIFO_FULL condition when reached.
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* Values range from 0 to 32.
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* @return 0 in case of success, negative error code otherwise.
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*/
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int adxl345_configure_fifo(const struct device *dev,
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enum adxl345_fifo_mode mode,
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enum adxl345_fifo_trigger trigger,
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uint16_t fifo_samples)
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{
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struct adxl345_dev_data *data = dev->data;
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uint8_t fifo_config;
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int ret;
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if (fifo_samples > 32) {
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return -EINVAL;
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}
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fifo_config = (ADXL345_FIFO_CTL_TRIGGER_MODE(trigger) |
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ADXL345_FIFO_CTL_MODE_MODE(mode) |
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ADXL345_FIFO_CTL_SAMPLES_MODE(fifo_samples));
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ret = adxl345_reg_write_byte(dev, ADXL345_FIFO_CTL_REG, fifo_config);
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if (ret) {
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return ret;
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}
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data->fifo_config.fifo_trigger = trigger;
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data->fifo_config.fifo_mode = mode;
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data->fifo_config.fifo_samples = fifo_samples;
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return 0;
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}
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/**
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* Set the mode of operation.
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* @param dev - The device structure.
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* @param op_mode - Mode of operation.
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* Accepted values: ADXL345_STANDBY
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* ADXL345_MEASURE
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* @return 0 in case of success, negative error code otherwise.
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*/
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int adxl345_set_op_mode(const struct device *dev, enum adxl345_op_mode op_mode)
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{
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return adxl345_reg_write_mask(dev, ADXL345_POWER_CTL_REG,
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ADXL345_POWER_CTL_MEASURE_MSK,
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ADXL345_POWER_CTL_MEASURE_MODE(op_mode));
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}
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/**
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* Set Output data rate.
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* @param dev - The device structure.
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* @param odr - Output data rate.
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* Accepted values: ADXL345_ODR_12HZ
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* ADXL345_ODR_25HZ
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* ADXL345_ODR_50HZ
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* ADXL345_ODR_100HZ
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* ADXL345_ODR_200HZ
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* ADXL345_ODR_400HZ
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* @return 0 in case of success, negative error code otherwise.
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*/
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static int adxl345_set_odr(const struct device *dev, enum adxl345_odr odr)
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{
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return adxl345_reg_write_mask(dev, ADXL345_RATE_REG,
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ADXL345_ODR_MSK,
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ADXL345_ODR_MODE(odr));
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}
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static int adxl345_attr_set_odr(const struct device *dev,
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enum sensor_channel chan,
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enum sensor_attribute attr,
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const struct sensor_value *val)
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{
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enum adxl345_odr odr;
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struct adxl345_dev_data *data = dev->data;
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switch (val->val1) {
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case 12:
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odr = ADXL345_ODR_12HZ;
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break;
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case 25:
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odr = ADXL345_ODR_25HZ;
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break;
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case 50:
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odr = ADXL345_ODR_50HZ;
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break;
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case 100:
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odr = ADXL345_ODR_100HZ;
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break;
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case 200:
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odr = ADXL345_ODR_200HZ;
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break;
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case 400:
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odr = ADXL345_ODR_400HZ;
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break;
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default:
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return -EINVAL;
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}
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int ret = adxl345_set_odr(dev, odr);
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if (ret == 0) {
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data->odr = odr;
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}
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return ret;
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}
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static int adxl345_attr_set(const struct device *dev,
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enum sensor_channel chan,
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enum sensor_attribute attr,
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const struct sensor_value *val)
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{
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switch (attr) {
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case SENSOR_ATTR_SAMPLING_FREQUENCY:
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return adxl345_attr_set_odr(dev, chan, attr, val);
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default:
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return -ENOTSUP;
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}
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}
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int adxl345_read_sample(const struct device *dev,
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struct adxl345_sample *sample)
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{
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int16_t raw_x, raw_y, raw_z;
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uint8_t axis_data[6], status1;
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if (!IS_ENABLED(CONFIG_ADXL345_TRIGGER)) {
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do {
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adxl345_get_status(dev, &status1, NULL);
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} while (!(ADXL345_STATUS_DATA_RDY(status1)));
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}
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int rc = adxl345_reg_read(dev, ADXL345_X_AXIS_DATA_0_REG, axis_data, 6);
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if (rc < 0) {
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LOG_ERR("Samples read failed with rc=%d\n", rc);
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return rc;
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}
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raw_x = axis_data[0] | (axis_data[1] << 8);
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raw_y = axis_data[2] | (axis_data[3] << 8);
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raw_z = axis_data[4] | (axis_data[5] << 8);
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sample->x = raw_x;
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sample->y = raw_y;
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sample->z = raw_z;
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return 0;
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}
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void adxl345_accel_convert(struct sensor_value *val, int16_t sample)
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{
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if (sample & BIT(9)) {
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sample |= ADXL345_COMPLEMENT;
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}
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val->val1 = ((sample * SENSOR_G) / 32) / 1000000;
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val->val2 = ((sample * SENSOR_G) / 32) % 1000000;
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}
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static int adxl345_sample_fetch(const struct device *dev,
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enum sensor_channel chan)
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{
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struct adxl345_dev_data *data = dev->data;
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struct adxl345_sample sample;
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uint8_t samples_count;
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int rc;
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data->sample_number = 0;
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rc = adxl345_reg_read_byte(dev, ADXL345_FIFO_STATUS_REG, &samples_count);
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if (rc < 0) {
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LOG_ERR("Failed to read FIFO status rc = %d\n", rc);
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return rc;
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}
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__ASSERT_NO_MSG(samples_count <= ARRAY_SIZE(data->bufx));
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for (uint8_t s = 0; s < samples_count; s++) {
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rc = adxl345_read_sample(dev, &sample);
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if (rc < 0) {
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LOG_ERR("Failed to fetch sample rc=%d\n", rc);
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return rc;
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}
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data->bufx[s] = sample.x;
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data->bufy[s] = sample.y;
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data->bufz[s] = sample.z;
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}
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return 0;
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}
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static int adxl345_channel_get(const struct device *dev,
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enum sensor_channel chan,
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struct sensor_value *val)
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{
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struct adxl345_dev_data *data = dev->data;
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if (data->sample_number >= ARRAY_SIZE(data->bufx)) {
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data->sample_number = 0;
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}
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switch (chan) {
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case SENSOR_CHAN_ACCEL_X:
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adxl345_accel_convert(val, data->bufx[data->sample_number]);
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data->sample_number++;
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break;
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case SENSOR_CHAN_ACCEL_Y:
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adxl345_accel_convert(val, data->bufy[data->sample_number]);
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data->sample_number++;
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break;
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case SENSOR_CHAN_ACCEL_Z:
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adxl345_accel_convert(val, data->bufz[data->sample_number]);
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data->sample_number++;
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break;
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case SENSOR_CHAN_ACCEL_XYZ:
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adxl345_accel_convert(val++, data->bufx[data->sample_number]);
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adxl345_accel_convert(val++, data->bufy[data->sample_number]);
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adxl345_accel_convert(val, data->bufz[data->sample_number]);
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data->sample_number++;
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static DEVICE_API(sensor, adxl345_api_funcs) = {
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.attr_set = adxl345_attr_set,
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.sample_fetch = adxl345_sample_fetch,
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.channel_get = adxl345_channel_get,
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#ifdef CONFIG_ADXL345_TRIGGER
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.trigger_set = adxl345_trigger_set,
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#endif
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#ifdef CONFIG_SENSOR_ASYNC_API
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.submit = adxl345_submit,
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.get_decoder = adxl345_get_decoder,
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#endif
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};
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#ifdef CONFIG_ADXL345_TRIGGER
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/**
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* Configure the INT1 and INT2 interrupt pins.
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* @param dev - The device structure.
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* @param int1 - INT1 interrupt pins.
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* @return 0 in case of success, negative error code otherwise.
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*/
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static int adxl345_interrupt_config(const struct device *dev,
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uint8_t int1)
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{
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int ret;
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const struct adxl345_dev_config *cfg = dev->config;
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ret = adxl345_reg_write_byte(dev, ADXL345_INT_MAP, int1);
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if (ret) {
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return ret;
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}
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ret = adxl345_reg_write_byte(dev, ADXL345_INT_ENABLE, int1);
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if (ret) {
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return ret;
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}
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uint8_t samples;
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ret = adxl345_reg_read_byte(dev, ADXL345_INT_MAP, &samples);
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ret = adxl345_reg_read_byte(dev, ADXL345_INT_ENABLE, &samples);
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#ifdef CONFIG_ADXL345_TRIGGER
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gpio_pin_interrupt_configure_dt(&cfg->interrupt,
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GPIO_INT_EDGE_TO_ACTIVE);
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#endif
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return 0;
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}
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#endif
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static int adxl345_init(const struct device *dev)
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{
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int rc;
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struct adxl345_dev_data *data = dev->data;
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#ifdef CONFIG_ADXL345_TRIGGER
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const struct adxl345_dev_config *cfg = dev->config;
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#endif
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uint8_t dev_id, full_res;
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data->sample_number = 0;
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if (!adxl345_bus_is_ready(dev)) {
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LOG_ERR("bus not ready");
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return -ENODEV;
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}
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rc = adxl345_reg_read_byte(dev, ADXL345_DEVICE_ID_REG, &dev_id);
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if (rc < 0 || dev_id != ADXL345_PART_ID) {
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LOG_ERR("Read PART ID failed: 0x%x\n", rc);
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return -ENODEV;
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}
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rc = adxl345_reg_write_byte(dev, ADXL345_FIFO_CTL_REG, ADXL345_FIFO_STREAM_MODE);
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if (rc < 0) {
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LOG_ERR("FIFO enable failed\n");
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return -EIO;
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}
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rc = adxl345_reg_write_byte(dev, ADXL345_DATA_FORMAT_REG, ADXL345_RANGE_8G);
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if (rc < 0) {
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LOG_ERR("Data format set failed\n");
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return -EIO;
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}
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data->selected_range = ADXL345_RANGE_8G;
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rc = adxl345_reg_write_byte(dev, ADXL345_RATE_REG, ADXL345_RATE_25HZ);
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if (rc < 0) {
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LOG_ERR("Rate setting failed\n");
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return -EIO;
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}
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#ifdef CONFIG_ADXL345_TRIGGER
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rc = adxl345_configure_fifo(dev, ADXL345_FIFO_STREAMED,
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ADXL345_INT2,
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SAMPLE_NUM);
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if (rc) {
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return rc;
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}
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#endif
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rc = adxl345_reg_write_byte(dev, ADXL345_POWER_CTL_REG, ADXL345_ENABLE_MEASURE_BIT);
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if (rc < 0) {
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LOG_ERR("Enable measure bit failed\n");
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return -EIO;
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}
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#ifdef CONFIG_ADXL345_TRIGGER
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rc = adxl345_init_interrupt(dev);
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if (rc < 0) {
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LOG_ERR("Failed to initialize interrupt!");
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return -EIO;
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}
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rc = adxl345_set_odr(dev, cfg->odr);
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if (rc) {
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return rc;
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}
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rc = adxl345_interrupt_config(dev, ADXL345_INT_MAP_WATERMARK_MSK);
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if (rc) {
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|
return rc;
|
|
}
|
|
#endif
|
|
|
|
rc = adxl345_reg_read_byte(dev, ADXL345_DATA_FORMAT_REG, &full_res);
|
|
uint8_t is_full_res_set = (full_res & ADXL345_DATA_FORMAT_FULL_RES) != 0;
|
|
|
|
data->is_full_res = is_full_res_set;
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_ADXL345_TRIGGER
|
|
#define ADXL345_CFG_IRQ(inst) \
|
|
.interrupt = GPIO_DT_SPEC_INST_GET(inst, int2_gpios),
|
|
#else
|
|
#define ADXL345_CFG_IRQ(inst)
|
|
#endif /* CONFIG_ADXL345_TRIGGER */
|
|
|
|
#define ADXL345_RTIO_SPI_DEFINE(inst) \
|
|
COND_CODE_1(CONFIG_SPI_RTIO, \
|
|
(SPI_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst), \
|
|
SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \
|
|
SPI_MODE_CPOL | SPI_MODE_CPHA, 0U);), \
|
|
())
|
|
|
|
#define ADXL345_RTIO_I2C_DEFINE(inst) \
|
|
COND_CODE_1(CONFIG_I2C_RTIO, \
|
|
(I2C_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst));), \
|
|
())
|
|
|
|
/* Conditionally set the RTIO size based on the presence of SPI/I2C
|
|
* lines 541 - 542.
|
|
* The sizes of sqe and cqe pools are increased due to the amount of
|
|
* multibyte reads needed for watermark using 31 samples
|
|
* (adx345_stram - line 203), using smaller amounts of samples
|
|
* to trigger an interrupt can decrease the pool sizes.
|
|
*/
|
|
#define ADXL345_RTIO_DEFINE(inst) \
|
|
/* Conditionally include SPI and/or I2C parts based on their presence */ \
|
|
COND_CODE_1(DT_INST_ON_BUS(inst, spi), \
|
|
(ADXL345_RTIO_SPI_DEFINE(inst)), \
|
|
()) \
|
|
COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \
|
|
(ADXL345_RTIO_I2C_DEFINE(inst)), \
|
|
()) \
|
|
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, spi_dt_spec) && \
|
|
DT_INST_NODE_HAS_PROP(inst, i2c_dt_spec), \
|
|
(RTIO_DEFINE(adxl345_rtio_ctx_##inst, 128, 128);), \
|
|
(RTIO_DEFINE(adxl345_rtio_ctx_##inst, 64, 64);)) \
|
|
|
|
#define ADXL345_CONFIG(inst) \
|
|
.odr = DT_INST_PROP(inst, odr), \
|
|
.fifo_config.fifo_mode = ADXL345_FIFO_STREAMED, \
|
|
.fifo_config.fifo_trigger = ADXL345_INT2, \
|
|
.fifo_config.fifo_samples = SAMPLE_NUM, \
|
|
.odr = ADXL345_RATE_25HZ, \
|
|
|
|
#define ADXL345_CONFIG_SPI(inst) \
|
|
{ \
|
|
.bus = {.spi = SPI_DT_SPEC_INST_GET(inst, \
|
|
SPI_WORD_SET(8) | \
|
|
SPI_TRANSFER_MSB | \
|
|
SPI_MODE_CPOL | \
|
|
SPI_MODE_CPHA, \
|
|
0)}, \
|
|
.bus_is_ready = adxl345_bus_is_ready_spi, \
|
|
.reg_access = adxl345_reg_access_spi, \
|
|
.bus_type = ADXL345_BUS_SPI, \
|
|
ADXL345_CONFIG(inst) \
|
|
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
|
|
(ADXL345_CFG_IRQ(inst)), ()) \
|
|
}
|
|
|
|
#define ADXL345_CONFIG_I2C(inst) \
|
|
{ \
|
|
.bus = {.i2c = I2C_DT_SPEC_INST_GET(inst)}, \
|
|
.bus_is_ready = adxl345_bus_is_ready_i2c, \
|
|
.reg_access = adxl345_reg_access_i2c, \
|
|
.bus_type = ADXL345_BUS_I2C, \
|
|
ADXL345_CONFIG(inst) \
|
|
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
|
|
(ADXL345_CFG_IRQ(inst)), ()) \
|
|
}
|
|
|
|
#define ADXL345_DEFINE(inst) \
|
|
IF_ENABLED(CONFIG_ADXL345_STREAM, (ADXL345_RTIO_DEFINE(inst))); \
|
|
static struct adxl345_dev_data adxl345_data_##inst = { \
|
|
COND_CODE_1(adxl345_iodev_##inst, (.rtio_ctx = &adxl345_rtio_ctx_##inst, \
|
|
.iodev = &adxl345_iodev_##inst,), ()) \
|
|
}; \
|
|
static const struct adxl345_dev_config adxl345_config_##inst = \
|
|
COND_CODE_1(DT_INST_ON_BUS(inst, spi), (ADXL345_CONFIG_SPI(inst)), \
|
|
(ADXL345_CONFIG_I2C(inst))); \
|
|
\
|
|
SENSOR_DEVICE_DT_INST_DEFINE(inst, adxl345_init, NULL, \
|
|
&adxl345_data_##inst, &adxl345_config_##inst, POST_KERNEL,\
|
|
CONFIG_SENSOR_INIT_PRIORITY, &adxl345_api_funcs); \
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(ADXL345_DEFINE)
|