e282b0ea84
The RTC subsystem in espressif's SOCs, among other tasks is responsible for clock selection for CPU and for low power domain clocks such as RTC_SLOW and RTC_FAST. This commit allows for proper clock source and rate selection for CPU, using the espressif,riscv and espressif,xtensa-lx6/7 bindings. It also enables clock selection for RTC_FAST and RTC_SLOW, that impacts some peripherals, such as rtc_timer. Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
65 lines
1.2 KiB
Text
65 lines
1.2 KiB
Text
/*
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* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <espressif/esp32s3/esp32s3_appcpu.dtsi>
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/ {
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model = "Espressif ESP32S3-DevkitM APPCPU";
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compatible = "espressif,esp32s3";
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chosen {
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zephyr,sram = &sram0;
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zephyr,ipc_shm = &shm0;
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zephyr,ipc = &ipm0;
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};
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};
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&trng0 {
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status = "okay";
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};
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&ipm0 {
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status = "okay";
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};
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&flash0 {
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Reserve 64kB for the bootloader */
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x00000000 0x00010000>;
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read-only;
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};
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/* Reserve 1024kB for the application in slot 0 */
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x00010000 0x00100000>;
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};
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/* Reserve 1024kB for the application in slot 1 */
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slot1_partition: partition@110000 {
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label = "image-1";
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reg = <0x00110000 0x00100000>;
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};
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/* Reserve 256kB for the scratch partition */
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scratch_partition: partition@210000 {
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label = "image-scratch";
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reg = <0x00210000 0x00040000>;
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};
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storage_partition: partition@250000 {
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label = "storage";
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reg = <0x00250000 0x00006000>;
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};
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};
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};
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