55caa7b743
Makes the designware spi driver consistent with other spi drivers by selecting HAS_DTS_SPI in the driver. This required adding spi nodes and dts fixups to several arc and x86 socs, as well as enabling those nodes in associated boards. Also refactors the driver to use the base address, interrupt number, and interrupt priority from dts. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
216 lines
4.5 KiB
Text
216 lines
4.5 KiB
Text
/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/i2c/i2c.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "snps,arcem4";
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reg = <1>;
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};
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core_intc: arcv2-intc {
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compatible = "snps,arcv2-intc";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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flash0: flash@DT_FLASH_ADDR {
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compatible = "soc-nv-flash";
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reg = <DT_FLASH_ADDR DT_FLASH_SIZE>;
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};
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sram0: memory@a8000400 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xa8000400 DT_SRAM_SIZE>;
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};
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dccm0: dccm@80000000 {
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device_type = "memory";
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compatible = "arc,dccm";
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reg = <0x80000000 DT_DCCM_SIZE>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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rtc: rtc@b0000400 {
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compatible = "intel,qmsi-rtc";
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reg = <0xb0000400 0x400>;
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clock-frequency = <32768>;
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interrupts = <47 1>;
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interrupt-parent = <&core_intc>;
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label = "RTC_0";
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};
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uart0: uart@b0002000 {
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compatible = "intel,qmsi-uart";
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reg = <0xb0002000 0x400>;
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interrupts = <41 0>;
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interrupt-parent = <&core_intc>;
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label = "UART_0";
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status = "disabled";
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};
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uart1: uart@b0002400 {
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compatible = "intel,qmsi-uart";
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reg = <0xb0002400 0x400>;
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interrupts = <42 0>;
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interrupt-parent = <&core_intc>;
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label = "UART_1";
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status = "disabled";
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};
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gpio0: gpio@80017800 {
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compatible = "intel,qmsi-ss-gpio";
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reg = <0x80017800 0x100>;
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interrupts = <20 1>;
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interrupt-parent = <&core_intc>;
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label = "GPIO_0";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@80017900 {
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compatible = "intel,qmsi-ss-gpio";
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reg = <0x80017900 0x100>;
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interrupts = <21 1>;
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interrupt-parent = <&core_intc>;
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label = "GPIO_1";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: gpio@b0000c00 {
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compatible = "intel,qmsi-gpio";
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reg = <0xb0000c00 0x400>;
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interrupts = <44 1>;
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interrupt-parent = <&core_intc>;
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label = "GPIO_2";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio3: gpio@b0800b00 {
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compatible = "intel,qmsi-gpio";
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reg = <0xb0800b00 0x400>;
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interrupts = <67 1>;
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interrupt-parent = <&core_intc>;
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label = "GPIO_3";
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gpio-controller;
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#gpio-cells = <2>;
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};
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i2c0: i2c@80012000 {
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compatible = "intel,qmsi-ss-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x80012000 0x100>;
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interrupts = <22 1>, <25 1>, <24 1>, <23 1>;
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interrupt-names = "error", "stop", "tx", "rx";
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interrupt-parent = <&core_intc>;
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label = "I2C_0";
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status = "disabled";
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};
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i2c1: i2c@80012100 {
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compatible = "intel,qmsi-ss-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x80012100 0x100>;
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interrupts = <26 1>, <29 1>, <28 1>, <27 1>;
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interrupt-names = "error", "stop", "tx", "rx";
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interrupt-parent = <&core_intc>;
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label = "I2C_1";
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status = "disabled";
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};
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i2c2: i2c@b0002800 {
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compatible = "intel,qmsi-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xb0002800 0x400>;
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interrupts = <36 1>;
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interrupt-parent = <&core_intc>;
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label = "I2C_2";
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status = "disabled";
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};
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i2c3: i2c@b0002c00 {
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compatible = "intel,qmsi-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xb0002c00 0x400>;
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interrupts = <37 1>;
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interrupt-parent = <&core_intc>;
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label = "I2C_3";
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status = "disabled";
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};
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spi0: spi@80010000 {
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compatible = "snps,designware-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x80010000 0x400>;
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interrupts = <30 2>, <31 2>, <32 2>;
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interrupt-names = "err-int", "rx-avail", "tx-req";
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interrupt-parent = <&core_intc>;
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label = "SPI_0";
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status = "disabled";
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};
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spi1: spi@80010100 {
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compatible = "snps,designware-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x80010100 0x400>;
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interrupts = <33 2>, <34 2>, <35 2>;
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interrupt-names = "err-int", "rx-avail", "tx-req";
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interrupt-parent = <&core_intc>;
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label = "SPI_1";
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status = "disabled";
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};
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adc0: adc@80015000 {
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compatible = "snps,dw-adc";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x80015000 0x05>;
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interrupts = <19 0>, <18 0>;
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interrupt-names = "normal", "error";
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interrupt-parent = <&core_intc>;
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label = "ADC_0";
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status = "disabled";
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};
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};
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};
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