5364783ba1
These are very similar devices to mt8195, minimal changes needed beyond boilerplate configuration. In the process, this reworks the board/soc layout to be HWMv2 compliant, with "adsp" becoming a CPU cluster beneath the SOC. So the name of the boards to west become e.g. "mt8195/mt8195/adsp" (which can be shortened to "mt8195//adsp" if desired). Note that the cpuclk driver is not yet ported, it works only with 8195 (the clocking/power architecture seems similar between the parts, but the graph of wells and clocks is different and historically these have been three separate drivers in SOF). The biggest changes are in the image/loader scripts, which needed some rework for cross-device portability. Signed-off-by: Andy Ross <andyross@google.com>
227 lines
8.2 KiB
Python
Executable file
227 lines
8.2 KiB
Python
Executable file
#!/usr/bin/env python
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# Copyright 2023 The ChromiumOS Authors
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# SPDX-License-Identifier: Apache-2.0
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import ctypes
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import sys
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import mmap
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import time
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import struct
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from glob import glob
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import re
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# MT8195 audio firmware load/debug gadget
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# Note that the hardware handling here is only partial: in practice
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# the audio DSP depends on clock and power well devices whose drivers
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# live elsewhere in the kernel. Those aren't duplicated here. Make
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# sure the DSP has been started by a working kernel driver first.
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#
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# See gen_img.py for docs on the image format itself. The way this
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# script works is to map the device memory regions and registers via
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# /dev/mem and copy the two segments while resetting the DSP.
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#
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# In the kernel driver, the address/size values come from devicetree.
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# But currently the MediaTek architecture is one kernel driver per SOC
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# (i.e. the devicetree values in the kenrel source are tied to the
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# specific SOC anyway), so it really doesn't matter and we hard-code
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# the addresses for simplicity.
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#
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# (For future reference: in /proc/device-tree on current ChromeOS
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# kernels, the host registers are a "cfg" platform resource on the
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# "adsp@10803000" node. The sram is likewise the "sram" resource on
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# that device node, and the two dram areas are "memory-region"
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# phandles pointing to "adsp_mem_region" and "adsp_dma_mem_region"
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# nodes under "/reserved-memory").
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FILE_MAGIC = 0xe463be95
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# Runtime mmap objects for each MAPPINGS entry
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maps = {}
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# Returns a string (e.g. "mt8195", "mt8186", "mt8188") if a supported
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# adsp is detected, or None if not
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def detect():
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compat = readfile(glob("/proc/device-tree/**/adsp@*/compatible",
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recursive=True)[0], "r")
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m = re.match(r'.*(mt\d{4})-dsp', compat)
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if m:
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return m.group(1)
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# Parse devicetree to find the MMIO mappings: there is an "adsp" node
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# (in various locations) with an array of named "reg" mappings. It
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# also refers by reference to reserved-memory regions of system
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# DRAM. Those don't have names, call them dram0/1 (dram1 is the main
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# region to which code is linked, dram0 is presumably a dma pool but
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# unused by current firmware). Returns a dict mapping name to a
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# (addr, size) tuple.
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def mappings():
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path = glob("/proc/device-tree/**/adsp@*/", recursive=True)[0]
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rnames = readfile(path + "reg-names", "r").split('\0')[:-1]
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regs = struct.unpack(f">{2 * len(rnames)}Q", readfile(path + "reg"))
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maps = { n : (regs[2*i], regs[2*i+1]) for i, n in enumerate(rnames) }
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for i, ph in enumerate(struct.unpack(">II", readfile(path + "memory-region"))):
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for rmem in glob("/proc/device-tree/reserved-memory/*/"):
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if struct.unpack(">I", readfile(rmem + "phandle"))[0] == ph:
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(addr, sz) = struct.unpack(">QQ", readfile(rmem + "reg"))
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maps[f"dram{i}"] = (addr, sz)
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break
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return maps
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# Register API for 8195
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class MT8195():
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def __init__(self, maps):
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# Create a Regs object for the registers
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r = Regs(ctypes.addressof(ctypes.c_int.from_buffer(maps["cfg"])))
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r.ALTRESETVEC = 0x0004 # Xtensa boot address
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r.RESET_SW = 0x0024 # Xtensa halt/reset/boot control
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r.PDEBUGBUS0 = 0x000c # Unclear, enabled by host, unused by SOF?
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r.SRAM_POOL_CON = 0x0930 # SRAM power control: low 4 bits (banks?) enable
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r.EMI_MAP_ADDR = 0x981c # == host SRAM mapping - 0x40000000 (controls MMIO map?)
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r.freeze()
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self.cfg = r
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def stop(self):
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self.cfg.RESET_SW |= 8 # Set RUNSTALL: halt CPU
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self.cfg.RESET_SW |= 3 # Set low two bits: "BRESET|DRESET"
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def start(self, boot_vector):
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self.stop()
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self.cfg.RESET_SW |= 0x10 # Enable "alternate reset" boot vector
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self.cfg.ALTRESETVEC = boot_vector
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self.cfg.RESET_SW &= ~3 # Release reset bits
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self.cfg.RESET_SW &= ~8 # Clear RUNSTALL: go!
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# Register API for 8186/8188
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class MT818x():
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def __init__(self, maps):
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# These have registers spread across two blocks
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cfg_base = ctypes.addressof(ctypes.c_int.from_buffer(maps["cfg"]))
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sec_base = ctypes.addressof(ctypes.c_int.from_buffer(maps["sec"]))
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self.cfg = Regs(cfg_base)
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self.cfg.SW_RSTN = 0x00
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self.cfg.IO_CONFIG = 0x0c
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self.cfg.freeze()
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self.sec = Regs(sec_base)
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self.sec.ALTVEC_C0 = 0x04
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self.sec.ALTVECSEL = 0x0c
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self.sec.freeze()
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def stop(self):
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self.cfg.IO_CONFIG |= (1<<31) # Set RUNSTALL to stop core
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time.sleep(0.1)
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self.cfg.SW_RSTN |= 0x11 # Assert reset: SW_RSTN_C0|SW_DBG_RSTN_C0
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# Note: 8186 and 8188 use different bits in ALTVECSEC, but
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# it's safe to write both to enable the alternate boot vector
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def start(self, boot_vector):
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self.cfg.IO_CONFIG |= (1<<31) # Set RUNSTALL
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self.sec.ALTVEC_C0 = boot_vector
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self.sec.ALTVECSEL = 0x03 # Enable alternate vector
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self.cfg.SW_RSTN |= 0x00000011 # Assert reset
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self.cfg.SW_RSTN &= 0xffffffee # Release reset
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self.cfg.IO_CONFIG &= 0x7fffffff # Clear RUNSTALL
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# Temporary logging protocol: watch the 1M null-terminated log
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# stream at 0x60700000 -- the top of the linkable region of
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# existing SOF firmware, before the heap. Nothing uses this
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# currently. Will be replaced by winstream very soon.
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def log():
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msg = b''
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dram = maps["dram1"]
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for i in range(0x700000, 0x800000):
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x = dram[i]
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if x == 0:
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sys.stdout.buffer.write(msg)
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sys.stdout.buffer.flush()
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msg = b''
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while x == 0:
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time.sleep(0.1)
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x = dram[i]
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msg += x.to_bytes(1, "little")
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sys.stdout.buffer.write(msg)
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sys.stdout.buffer.flush()
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# (Cribbed from cavstool.py)
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class Regs:
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def __init__(self, base_addr):
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vars(self)["base_addr"] = base_addr
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vars(self)["ptrs"] = {}
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vars(self)["frozen"] = False
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def freeze(self):
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vars(self)["frozen"] = True
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def __setattr__(self, name, val):
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if not self.frozen and name not in self.ptrs:
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addr = self.base_addr + val
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self.ptrs[name] = ctypes.c_uint32.from_address(addr)
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else:
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self.ptrs[name].value = val
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def __getattr__(self, name):
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return self.ptrs[name].value
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def readfile(f, mode="rb"):
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return open(f, mode).read()
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def le4(bstr):
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assert len(bstr) == 4
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return struct.unpack("<I", bstr)[0]
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def main():
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dsp = detect()
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assert dsp
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# Probe devicetree for mappable memory regions
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mmio = mappings()
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# Open device and establish mappings
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devmem_fd = open("/dev/mem", "wb+")
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for mp in mmio:
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paddr = mmio[mp][0]
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mapsz = mmio[mp][1]
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mapsz = int((mapsz + 4095) / 4096) * 4096
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maps[mp] = mmap.mmap(devmem_fd.fileno(), mapsz, offset=paddr,
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flags=mmap.MAP_SHARED, prot=mmap.PROT_WRITE|mmap.PROT_READ)
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if dsp == "mt8195":
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dev = MT8195(maps)
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elif dsp in ("mt8186", "mt8188"):
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dev = MT818x(maps)
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if sys.argv[1] == "load":
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dat = open(sys.argv[2], "rb").read()
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assert le4(dat[0:4])== FILE_MAGIC
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sram_len = le4(dat[4:8])
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boot_vector = le4(dat[8:12])
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sram = dat[12:12+sram_len]
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dram = dat[12 + sram_len:]
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assert len(sram) <= mmio["sram"][1]
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assert len(dram) <= mmio["dram1"][1]
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# Stop the device and write the regions. Note that we don't
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# zero-fill SRAM, as that's been observed to reboot the host
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# (!!) on mt8186 when the writes near the end of the 512k
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# region.
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# pylint: disable=consider-using-enumerate
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for i in range(sram_len):
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maps["sram"][i] = sram[i]
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#for i in range(sram_len, mmio["sram"][1]):
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# maps["sram"][i] = 0
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for i in range(len(dram)):
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maps["dram1"][i] = dram[i]
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for i in range(len(dram), mmio["dram1"][1]):
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maps["dram1"][i] = 0
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dev.start(boot_vector)
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log()
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elif sys.argv[1] == "log":
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log()
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elif sys.argv[1] == "dump":
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sz = mmio[sys.argv[2]][1]
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mm = maps[sys.argv[2]]
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sys.stdout.buffer.write(mm[0:sz])
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else:
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print(f"Usage: {sys.argv[0]} log | load <file>")
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if __name__ == "__main__":
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main()
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