a7096fac7d
When CONFIG_RISCV_VECTORED_MODE is disabled, CLIC claims interrupts using CSR 'mnxti' and handles all pending interrupts before exiting the ISR. When CONFIG_RISCV_VECTORED_MODE is enabled, all interrupts use vector mode and are claimed automatically. The RISC-V common ISR is used for interrupts hooked into SW ISR table, but it only handle one pending interrupt per ISR. This commit enhances CLIC to set vector mode for direct ISRs only and use the CLIC common entry for regular ISRs to handles multiple pending interrupts in an ISR. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
37 lines
1 KiB
Text
37 lines
1 KiB
Text
# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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config NUCLEI_ECLIC
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bool "Enhanced Core Local Interrupt Controller (ECLIC)"
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default y
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depends on DT_HAS_NUCLEI_ECLIC_ENABLED
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select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
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select CLIC_SMCLICSHV_EXT if RISCV_VECTORED_MODE
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help
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Interrupt controller for Nuclei SoC core.
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config NRFX_CLIC
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bool "VPR Core Local Interrpt Controller (CLIC)"
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default y
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depends on DT_HAS_NORDIC_NRF_CLIC_ENABLED
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select GEN_IRQ_VECTOR_TABLE
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help
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Interrupt controller for Nordic VPR cores.
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config CLIC_SMCLICSHV_EXT
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bool
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help
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The selective hardware vectoring extension gives users the flexibility
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to select the behavior for each interrupt. The CLIC driver needs to
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implement the riscv_clic_irq_vector_set() function.
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if NUCLEI_ECLIC
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config LEGACY_CLIC
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bool "Use the legacy clic specification"
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depends on RISCV_HAS_CLIC
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help
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Enables legacy clic, where smclicshv extension is not supported and
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hardware vectoring is set via mode bits of mtvec.
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endif # NUCLEI_ECLIC
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