528c960ae7
In ARC's SecureShield, a new secure mode (currently only em) is added. The secure/normal mode is orthogonal to kernel/user mode. The differences between secure mode and normal mode are following: * different irq stack frame. so need to change the definition of _irq_stack_frame, assembly code. * new aux regs, e.g, secure status(SEC_STAT), secure vector base (VECT_BASE_S) * interrupts and exceptions, secure mode has its own vector base; interrupt can be configured as secure or normal through the interrupt priority aux reg. * secure timers. Two secure timers (secure timer 0 and timer 1) are added.Here, for simplicity and backwards compatibility original internal timers (timer 0 and timer1) are used as sys clock of zephyr * on reset, the processor is in secure mode and secure vector base is used. Note: the mix of secure and normal mode is not supported, i.e. it's assumed that the processor is always in secure mode. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
166 lines
3.5 KiB
C
166 lines
3.5 KiB
C
/* arcv2_irq_unit.h - ARCv2 Interrupt Unit device driver */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ARC_V2_IRQ_UNIT__H
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#define _ARC_V2_IRQ_UNIT__H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* configuration flags for interrupt unit */
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#define _ARC_V2_INT_DISABLE 0
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#define _ARC_V2_INT_ENABLE 1
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#define _ARC_V2_INT_LEVEL 0
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#define _ARC_V2_INT_PULSE 1
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#ifndef _ASMLANGUAGE
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/*
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* WARNING:
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*
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* All APIs provided by this file must be invoked with INTERRUPTS LOCKED. The
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* APIs themselves are writing the IRQ_SELECT, selecting which IRQ's registers
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* it wants to write to, then write to them: THIS IS NOT AN ATOMIC OPERATION.
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*
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* Not locking the interrupts inside of the APIs allows a caller to:
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*
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* - lock interrupts
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* - call many of these APIs
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* - unlock interrupts
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*
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* thus being more efficient then if the APIs themselves would lock
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* interrupts.
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*/
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/*
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* @brief Enable/disable interrupt
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*
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* Enables or disables the specified interrupt
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*
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* @return N/A
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*/
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static inline void _arc_v2_irq_unit_irq_enable_set(
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int irq,
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unsigned char enable
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)
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{
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_ENABLE, enable);
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}
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/*
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* @brief Enable interrupt
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*
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* Enables the specified interrupt
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*
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* @return N/A
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*/
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static inline void _arc_v2_irq_unit_int_enable(int irq)
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{
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_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_ENABLE);
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}
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/*
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* @brief Disable interrupt
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*
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* Disables the specified interrupt
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*
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* @return N/A
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*/
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static inline void _arc_v2_irq_unit_int_disable(int irq)
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{
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_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_DISABLE);
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}
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/*
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* @brief Set interrupt priority
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*
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* Set the priority of the specified interrupt
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*
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* @return N/A
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*/
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static inline void _arc_v2_irq_unit_prio_set(int irq, unsigned char prio)
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{
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
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#ifdef CONFIG_ARC_HAS_SECURE
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/* if ARC has secure mode, all interrupt should be secure */
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_PRIORITY, prio |
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_ARC_V2_IRQ_PRIORITY_SECURE);
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#else
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_PRIORITY, prio);
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#endif
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}
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/*
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* @brief Set interrupt sensitivity
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*
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* Set the sensitivity of the specified interrupt to either
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* _ARC_V2_INT_LEVEL or _ARC_V2_INT_PULSE. Level interrupts will remain
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* asserted until the interrupt handler clears the interrupt at the peripheral.
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* Pulse interrupts self-clear as the interrupt handler is entered.
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*
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* @return N/A
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*/
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static inline void _arc_v2_irq_unit_sensitivity_set(int irq, int s)
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{
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_TRIGGER, s);
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}
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/*
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* @brief Sets an IRQ line to level/pulse trigger
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*
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* Sets the IRQ line <irq> to trigger an interrupt based on the level or the
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* edge of the signal. Valid values for <trigger> are _ARC_V2_INT_LEVEL and
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* _ARC_V2_INT_PULSE.
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*
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* @return N/A
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*/
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void _arc_v2_irq_unit_trigger_set(int irq, unsigned int trigger);
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/*
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* @brief Returns an IRQ line trigger type
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*
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* Gets the IRQ line <irq> trigger type.
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* Valid values for <trigger> are _ARC_V2_INT_LEVEL and _ARC_V2_INT_PULSE.
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*
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* @return N/A
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*/
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unsigned int _arc_v2_irq_unit_trigger_get(int irq);
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/*
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* @brief Send EOI signal to interrupt unit
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*
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* This routine sends an EOI (End Of Interrupt) signal to the interrupt unit
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* to clear a pulse-triggered interrupt.
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*
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* Interrupts must be locked or the ISR operating at P0 when invoking this
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* function.
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*
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* @return N/A
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*/
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void _arc_v2_irq_unit_int_eoi(int irq);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ARC_V2_IRQ_UNIT__H */
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