Andy Ross 5183e5e606 soc/intel_adsp: Fix region cacheability for MP cores ... On MP cores that don't come through the core entry point (e.g. TGL/v2.5) we reach C code with hardware defaults for the RPO/TLB settings. Set these up correctly on entry. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2021-09-03 07:19:34 -04:00
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esp32	soc: esp32: Fix placement for system heap	2021-08-31 15:36:12 -04:00
esp32s2	esp32s2: drivers: gpio: add gpio support	2021-08-27 17:34:41 -04:00
intel_adsp	soc/intel_adsp: Fix region cacheability for MP cores	2021-09-03 07:19:34 -04:00
intel_s1000	linker: xtensa: move IDT_LIST region	2021-08-25 18:08:36 -04:00
nxp_adsp	arch: xtensa: modify asm for interrupt sections	2021-08-28 23:27:02 -04:00
sample_controller	linker: align _image_text_start/end/size linker symbols name	2021-08-28 08:48:03 -04:00
CMakeLists.txt	soc/xtensa/intel_adsp: Upstream updates	2020-10-21 06:38:53 -04:00