f216c434d0
For Nuclei ECLIC, the interrupt level (mintstatus.MIL) is restored from the previous interrupt level (mcause.MPIL) only if mcause.interrupt is set. This behavior is not defined in the RISC-V CLIC spec. If an ISR causes a context switch and mcause.interrupt is not set in the next context (e.g. the next context is yielded from ecall), interrupts will be masked after MRET because the interrupt level is not restored. Use SOC-specific context to set mcause.interrupt to ensure the interrupt level is restored correctly. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com> |
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| .. | ||
| common | ||
| gd32a50x | ||
| gd32e10x | ||
| gd32e50x | ||
| gd32f3x0 | ||
| gd32f4xx | ||
| gd32f403 | ||
| gd32l23x | ||
| gd32vf103 | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.defconfig | ||
| Kconfig.soc | ||
| soc.yml | ||