4e1179bba5
Adding watchdog driver for sam SoC. The current implemntation just diables the watchdog on device boot. This PR adds the following support for SAM3X, SAM4S and SAME70 1. Activate processor reset 2. Activate all reset 3. Generate interrupt on watchdog timer expiration. Signed-off-by: Subramanian Meenakshi Sundaram <subbu147@gmail.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
57 lines
3.5 KiB
C
57 lines
3.5 KiB
C
/* This file is a temporary workaround for mapping of the generated information
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* to the current driver definitions. This will be removed when the drivers
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* are modified to handle the generated information, or the mapping of
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* generated data matches the driver definitions.
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*/
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/* SoC level DTS fixup file */
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define CONFIG_GPIO_SAM_PORTA_LABEL ATMEL_SAM_GPIO_400E0E00_LABEL
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#define CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS
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#define CONFIG_GPIO_SAM_PORTA_IRQ ATMEL_SAM_GPIO_400E0E00_IRQ_0
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#define CONFIG_GPIO_SAM_PORTA_IRQ_PRIO ATMEL_SAM_GPIO_400E0E00_IRQ_0_PRIORITY
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#define CONFIG_GPIO_SAM_PORTA_PERIPHERAL_ID ATMEL_SAM_GPIO_400E0E00_PERIPHERAL_ID
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#define CONFIG_GPIO_SAM_PORTB_LABEL ATMEL_SAM_GPIO_400E1000_LABEL
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#define CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS ATMEL_SAM_GPIO_400E1000_BASE_ADDRESS
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#define CONFIG_GPIO_SAM_PORTB_IRQ ATMEL_SAM_GPIO_400E1000_IRQ_0
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#define CONFIG_GPIO_SAM_PORTB_IRQ_PRIO ATMEL_SAM_GPIO_400E1000_IRQ_0_PRIORITY
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#define CONFIG_GPIO_SAM_PORTB_PERIPHERAL_ID ATMEL_SAM_GPIO_400E1000_PERIPHERAL_ID
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#define CONFIG_GPIO_SAM_PORTC_LABEL ATMEL_SAM_GPIO_400E1200_LABEL
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#define CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS ATMEL_SAM_GPIO_400E1200_BASE_ADDRESS
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#define CONFIG_GPIO_SAM_PORTC_IRQ ATMEL_SAM_GPIO_400E1200_IRQ_0
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#define CONFIG_GPIO_SAM_PORTC_IRQ_PRIO ATMEL_SAM_GPIO_400E1200_IRQ_0_PRIORITY
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#define CONFIG_GPIO_SAM_PORTC_PERIPHERAL_ID ATMEL_SAM_GPIO_400E1200_PERIPHERAL_ID
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#define CONFIG_I2C_0_BASE_ADDRESS ATMEL_SAM_I2C_TWI_40018000_BASE_ADDRESS
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#define CONFIG_I2C_0_NAME ATMEL_SAM_I2C_TWI_40018000_LABEL
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#define CONFIG_I2C_0_BITRATE ATMEL_SAM_I2C_TWI_40018000_CLOCK_FREQUENCY
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#define CONFIG_I2C_0_IRQ ATMEL_SAM_I2C_TWI_40018000_IRQ_0
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#define CONFIG_I2C_0_IRQ_PRI ATMEL_SAM_I2C_TWI_40018000_IRQ_0_PRIORITY
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#define CONFIG_I2C_0_PERIPHERAL_ID ATMEL_SAM_I2C_TWI_40018000_PERIPHERAL_ID
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#define CONFIG_I2C_1_BASE_ADDRESS ATMEL_SAM_I2C_TWI_4001C000_BASE_ADDRESS
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#define CONFIG_I2C_1_NAME ATMEL_SAM_I2C_TWI_4001C000_LABEL
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#define CONFIG_I2C_1_BITRATE ATMEL_SAM_I2C_TWI_4001C000_CLOCK_FREQUENCY
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#define CONFIG_I2C_1_IRQ ATMEL_SAM_I2C_TWI_4001C000_IRQ_0
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#define CONFIG_I2C_1_IRQ_PRI ATMEL_SAM_I2C_TWI_4001C000_IRQ_0_PRIORITY
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#define CONFIG_I2C_1_PERIPHERAL_ID ATMEL_SAM_I2C_TWI_4001C000_PERIPHERAL_ID
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#define CONFIG_UART_SAM_PORT_0_NAME ATMEL_SAM_UART_400E0600_LABEL
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#define CONFIG_UART_SAM_PORT_0_BAUD_RATE ATMEL_SAM_UART_400E0600_CURRENT_SPEED
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#define CONFIG_UART_SAM_PORT_0_IRQ ATMEL_SAM_UART_400E0600_IRQ_0
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#define CONFIG_UART_SAM_PORT_0_IRQ_PRIO ATMEL_SAM_UART_400E0600_IRQ_0_PRIORITY
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#define CONFIG_UART_SAM_PORT_1_NAME ATMEL_SAM_UART_400E0800_LABEL
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#define CONFIG_UART_SAM_PORT_1_BAUD_RATE ATMEL_SAM_UART_400E0800_CURRENT_SPEED
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#define CONFIG_UART_SAM_PORT_1_IRQ ATMEL_SAM_UART_400E0800_IRQ_0
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#define CONFIG_UART_SAM_PORT_1_IRQ_PRIO ATMEL_SAM_UART_400E0800_IRQ_0_PRIORITY
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#define CONFIG_USART_SAM_PORT_0_NAME ATMEL_SAM_USART_40024000_LABEL
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#define CONFIG_USART_SAM_PORT_0_BAUD_RATE ATMEL_SAM_USART_40024000_CURRENT_SPEED
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#define CONFIG_USART_SAM_PORT_1_NAME ATMEL_SAM_USART_40028000_LABEL
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#define CONFIG_USART_SAM_PORT_1_BAUD_RATE ATMEL_SAM_USART_40028000_CURRENT_SPEED
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#define CONFIG_WDT_SAM_IRQ ATMEL_SAM_WATCHDOG_400E1450_IRQ_0
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#define CONFIG_WDT_SAM_IRQ_PRIORITY ATMEL_SAM_WATCHDOG_400E1450_IRQ_0_PRIORITY
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#define CONFIG_WDT_SAM_LABEL ATMEL_SAM_WATCHDOG_400E1450_LABEL
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#define CONFIG_WDT_SAM_BASE_ADDRESS ATMEL_SAM_WATCHDOG_400E1450_BASE_ADDRESS
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/* End of SoC Level DTS fixup file */
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