4d1139de91
Microchip MEC was configuring the kernel timer tick rate at the board level instead of the SoC level. We unify all this by moving the Kconfig logic out of the board level into each mec chip. We also derive SYS_CLOCK_HW_TICKS_PER_SEC from the device tree node enabled for the kernel timer: Microchip's 32 KHz RTOT timer or Cortex-M4 SYSTICK. The soc kconfig rules are loading all mec subdirectories for every build causing warnings when building new socs with this change. We made the changes for all the mec chips. Signed-off-by: Scott Worley <scott.worley@microchip.com>
99 lines
2.6 KiB
Text
99 lines
2.6 KiB
Text
# Microchip MEC1501 MCU core series
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# Copyright (c) 2018 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_MEC15XX
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select ARM
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select HAS_PM
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select SOC_EARLY_INIT_HOOK
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config SOC_MEC1501_HSZ
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select HAS_MEC_HAL
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if SOC_SERIES_MEC15XX
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config SOC_MEC1501_PROC_CLK_DIV
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int "PROC_CLK_DIV"
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default 1
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range 1 48
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help
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This divisor defines a ratio between processor clock (HCLK)
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and master clock (MCK):
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HCLK = MCK / PROC_CLK_DIV
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Allowed divider values: 1, 3, 4, 16, and 48.
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config SOC_MEC1501_VTR3_1_8V
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bool "VTR3 power rail is tied to 1.8V"
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help
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Set this is if VTR3 power sourcejumper in the board is changed.
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config SOC_MEC1501_VCI_PINS_AS_GPIOS
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bool "Use VCI block pins as GPIOS"
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default y
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help
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By default these pins are not GPIOs, but HW controlled.
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Set this if VCI pin block HW logic is not required in the board
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design.
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choice
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prompt "MEC1501 debug interface general configuration"
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default SOC_MEC1501_DEBUG_WITHOUT_TRACING
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depends on SOC_SERIES_MEC15XX
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help
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Select Debug SoC interface support for MEC15xx SoC family
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config SOC_MEC1501_DEBUG_DISABLED
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bool "Disable debug support"
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help
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Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST#
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pin is ignored. All other JTAG pins can be used as GPIOs
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or other non-JTAG alternate functions.
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config SOC_MEC1501_DEBUG_WITHOUT_TRACING
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bool "Debug support via Serial wire debug"
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help
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JTAG port in SWD mode. UART2 and ADC00-03 can be used.
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config SOC_MEC1501_DEBUG_AND_TRACING
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bool "Debug support via Serial wire debug with tracing enabled"
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help
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JTAG port is enabled in SWD mode. Refer to tracing options
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to see if ADC00-03 can be used or not.
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endchoice
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choice
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prompt "MEC1501 debug interface trace configuration"
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default SOC_MEC1501_DEBUG_AND_ETM_TRACING
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depends on SOC_MEC1501_DEBUG_AND_TRACING
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help
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Select tracing mode for debug interface
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config SOC_MEC1501_DEBUG_AND_ETM_TRACING
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bool "Debug support via Serial wire debug"
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help
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JTAG port in SWD mode and SWV as tracing method.
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UART2 can be used, but ADC00-03 cannot.
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config SOC_MEC1501_DEBUG_AND_SWV_TRACING
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bool "debug support via Serial Wire Debug and Viewer"
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help
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JTAG port in SWD mode and SWV as tracing method.
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UART2 cannot be used. ADC00-03 can be used.
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endchoice
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# GPIO initialization depends on SOC initialization, which happen at
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# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be
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# higher than that.
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if GPIO
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config GPIO_INIT_PRIORITY
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default 41
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endif # GPIO
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endif # SOC_SERIES_MEC15XX
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