290 lines
6.3 KiB
Text
290 lines
6.3 KiB
Text
/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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/* Dummy pinctrl node, filled with pin mux options at board level */
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pinctrl: pinctrl {
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compatible = "nxp,port-pinctrl";
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status = "okay";
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};
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soc {
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edma0: dma-controller@40080000 {
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#dma-cells = <2>;
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compatible = "nxp,mcux-edma";
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nxp,version = <4>;
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dma-channels = <4>;
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dma-requests = <66>;
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reg = <0x40080000 0x1000>;
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interrupts = <2 0>, <3 0>, <4 0>, <5 0>;
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no-error-irq;
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status = "disabled";
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};
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flexpwm0: flexpwm@400a9000 {
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compatible = "nxp,flexpwm";
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reg = <0x400a9000 0x1000>;
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interrupt-names = "RELOAD-ERROR", "FAULT";
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interrupts = <44 0>, <45 0>;
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flexpwm0_pwm0: pwm0 {
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compatible = "nxp,imx-pwm";
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index = <0>;
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interrupts = <46 0>;
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#pwm-cells = <3>;
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clocks = <&syscon MCUX_BUS_CLK>;
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nxp,prescaler = <128>;
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status = "disabled";
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run-in-wait;
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};
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flexpwm0_pwm1: pwm1 {
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compatible = "nxp,imx-pwm";
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index = <1>;
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interrupts = <47 0>;
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#pwm-cells = <3>;
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clocks = <&syscon MCUX_BUS_CLK>;
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nxp,prescaler = <128>;
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status = "disabled";
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run-in-wait;
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};
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flexpwm0_pwm2: pwm2 {
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compatible = "nxp,imx-pwm";
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index = <2>;
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interrupts = <48 0>;
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#pwm-cells = <3>;
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clocks = <&syscon MCUX_BUS_CLK>;
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nxp,prescaler = <128>;
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status = "disabled";
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run-in-wait;
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};
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};
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fmu: flash-controller@40095000 {
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compatible = "nxp,msf1";
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reg = <0x40095000 0x1000>;
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interrupts = <12 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 DT_SIZE_K(128)>;
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erase-block-size = <8192>;
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write-block-size = <128>;
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};
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};
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gpio0: gpio@40102000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40102000 0x1000>;
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interrupts = <71 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porta>;
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};
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gpio1: gpio@40103000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40103000 0x1000>;
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interrupts = <72 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portb>;
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};
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gpio2: gpio@40104000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40104000 0x1000>;
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interrupts = <73 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portc>;
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};
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gpio3: gpio@40105000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40105000 0x1000>;
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interrupts = <74 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portd>;
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};
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lpadc0: lpadc@400af000 {
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compatible = "nxp,lpc-lpadc";
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reg = <0x400af000 0x1000>;
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interrupts = <62 0>;
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status = "disabled";
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clk-divider = <1>;
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clk-source = <0>;
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voltage-ref= <2>;
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calibration-average = <128>;
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power-level = <0>;
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offset-value-a = <0>;
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offset-value-b = <0>;
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#io-channel-cells = <1>;
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clocks = <&syscon MCUX_LPADC1_CLK>;
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};
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lpcmp0: lpcmp@400b1000 {
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compatible = "nxp,lpcmp";
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reg = <0x400b1000 0x1000>;
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interrupts = <64 0>;
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status = "disabled";
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#io-channel-cells = <2>;
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};
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lpcmp1: lpcmp@400b2000 {
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compatible = "nxp,lpcmp";
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reg = <0x400b2000 0x1000>;
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interrupts = <65 0>;
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status = "disabled";
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#io-channel-cells = <2>;
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};
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lpi2c0: i2c@4009a000 {
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compatible = "nxp,lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4009a000 0x1000>;
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interrupts = <26 0>;
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clocks = <&syscon MCUX_LPI2C0_CLK>;
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status = "disabled";
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};
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lpspi0: spi@4009c000 {
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compatible = "nxp,lpspi";
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reg = <0x4009c000 0x1000>;
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interrupts = <28 0>;
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clocks = <&syscon MCUX_LPSPI0_CLK>;
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tx-fifo-size = <4>;
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rx-fifo-size = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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lpspi1: spi@4009d000 {
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compatible = "nxp,lpspi";
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reg = <0x4009d000 0x1000>;
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interrupts = <29 0>;
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clocks = <&syscon MCUX_LPSPI1_CLK>;
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tx-fifo-size = <4>;
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rx-fifo-size = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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lpuart0: lpuart@4009f000 {
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compatible = "nxp,lpuart";
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status = "disabled";
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reg = <0x4009f000 0x1000>;
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interrupts = <31 0>;
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clocks = <&syscon MCUX_LPUART0_CLK>;
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/* DMA channels 0 and 1, muxed to LPUART0 RX and TX */
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dmas = <&edma0 0 21>, <&edma0 1 22>;
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dma-names = "rx", "tx";
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};
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lpuart1: lpuart@400a0000 {
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compatible = "nxp,lpuart";
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status = "disabled";
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reg = <0x400a0000 0x1000>;
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interrupts = <32 0>;
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clocks = <&syscon MCUX_LPUART1_CLK>;
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/* DMA channels 2 and 3, muxed to LPUART1 RX and TX */
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dmas = <&edma0 2 23>, <&edma0 3 24>;
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dma-names = "rx", "tx";
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};
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lpuart2: lpuart@400a1000 {
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compatible = "nxp,lpuart";
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status = "disabled";
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reg = <0x400a1000 0x1000>;
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interrupts = <33 0>;
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clocks = <&syscon MCUX_LPUART2_CLK>;
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/* DMA channels 2 and 3, muxed to LPUART2 RX and TX */
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dmas = <&edma0 2 25>, <&edma0 3 26>;
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dma-names = "rx", "tx";
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};
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porta: pinmux@400bc000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400bc000 0x1000>;
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clocks = <&syscon MCUX_PORT0_CLK>;
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};
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portb: pinmux@400bd000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400bd000 0x1000>;
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clocks = <&syscon MCUX_PORT1_CLK>;
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};
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portc: pinmux@400be000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400be000 0x1000>;
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clocks = <&syscon MCUX_PORT2_CLK>;
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};
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portd: pinmux@400bf000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400bf000 0x1000>;
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clocks = <&syscon MCUX_PORT3_CLK>;
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};
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sramx: memory@4000000 {
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compatible = "mmio-sram";
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reg = <0x4000000 DT_SIZE_K(8)>;
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(24)>;
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};
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syscon: syscon@40091000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x40091000 0x4000>;
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#clock-cells = <1>;
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reset: reset {
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compatible = "nxp,lpc-syscon-reset";
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#reset-cells = <1>;
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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