41d5808321
Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
26 lines
552 B
Text
26 lines
552 B
Text
#
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# Copyright (c) 2017, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_FAMILY_IMX
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bool
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# omit prompt to signify a "hidden" option
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default n
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if SOC_FAMILY_IMX
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config SOC_FAMILY
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string
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default "nxp_imx"
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endif
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source "arch/arm/soc/nxp_imx/*/Kconfig.soc"
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config SOC_PART_NUMBER
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string
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default SOC_PART_NUMBER_IMX_RT if SOC_SERIES_IMX_RT
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help
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This string holds the full part number of the SoC. It is a hidden option
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that you should not set directly. The part number selection choice defines
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the default value for this string.
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