Tomasz Bursztyka 4047b793c8 drivers/interrupt_controller: Generate proper MSI address on VT-D ... SHV bit depends on the number of vectors allocated. If it's facing a multi-vector MSI array, it will set the bit. If not the bit must be 0. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>		2022-01-07 10:47:27 -05:00
..
arc	soc: arc: fix ARC_HAS_ACCL_REGS settings	2021-12-02 11:32:14 -06:00
arm	arch: cortex_m: Fix dwt cyccnt assert	2021-12-10 12:27:49 +01:00
arm64	xenvm: arm64: add Xen Enlighten and event channel support	2021-12-07 12:15:38 -05:00
common	cmake: CMake linker script generator pass handling	2021-11-08 20:45:07 +01:00
nios2	arch: nios2: Fix 10.4 violations	2021-04-10 09:59:37 -04:00
posix	pm: Remove unused parameter	2021-11-17 11:15:49 -05:00
riscv	arch: riscv: ARCH_EXCEPT macro	2022-01-01 07:38:20 -05:00
sparc	arch/sparc: Add hook for CONFIG_SCHED_THREAD_USAGE accounting in ISRs	2021-11-08 21:32:20 -05:00
x86	drivers/interrupt_controller: Generate proper MSI address on VT-D	2022-01-07 10:47:27 -05:00
xtensa	soc/intel_adsp: Unify Xtensa CPU reset between cores	2021-12-14 18:43:05 -06:00
CMakeLists.txt	cmake: fix include directories to work with out-of-tree arch	2020-08-05 08:06:07 -04:00
Kconfig	coredump: add support for RISC-V	2021-12-08 08:54:32 -05:00