4192254ef2
Added properties to support the core interrupt controller on the NIOS2 cpu cores and enable that support for the NS16550 UART. We rename some compatibles so that the cpu core compatibles is unique. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
31 lines
431 B
Text
31 lines
431 B
Text
/* SPDX-License-Identifier: Apache-2.0 */
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/dts-v1/;
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#include <nios2f.dtsi>
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/ {
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model = "altera_max10";
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compatible = "altera,nios2-max10";
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aliases {
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uart-0 = &uart0;
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <I2C_BITRATE_ULTRA>;
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};
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