3842c60ce3
Add the clock driver for the STM32L4 series. Change-Id: Icdf79061f163d8d00187b382d1564422fb875c5b Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
186 lines
4.5 KiB
C
186 lines
4.5 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 BayLibre, SAS
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _STM32L4X_CLOCK_H_
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#define _STM32L4X_CLOCK_H_
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/**
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* @brief Driver for Reset & Clock Control of STM32L4x6 family processor.
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*/
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enum {
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STM32L4X_RCC_CFG_PLL_SRC_MSI = 0x1,
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STM32L4X_RCC_CFG_PLL_SRC_HSI = 0x2,
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STM32L4X_RCC_CFG_PLL_SRC_HSE = 0x3,
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};
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enum {
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STM32L4X_RCC_CFG_PLL_Q_R_0 = 0x1,
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STM32L4X_RCC_CFG_PLL_Q_R_2 = 0x2,
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};
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enum {
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STM32L4X_RCC_CFG_SYSCLK_SRC_MSI = 0x0,
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STM32L4X_RCC_CFG_SYSCLK_SRC_HSI = 0x1,
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STM32L4X_RCC_CFG_SYSCLK_SRC_HSE = 0x2,
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STM32L4X_RCC_CFG_SYSCLK_SRC_PLL = 0x3,
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};
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enum {
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STM32L4X_RCC_CFG_HCLK_DIV_0 = 0x0,
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STM32L4X_RCC_CFG_HCLK_DIV_2 = 0x4,
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STM32L4X_RCC_CFG_HCLK_DIV_4 = 0x5,
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STM32L4X_RCC_CFG_HCLK_DIV_8 = 0x6,
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STM32L4X_RCC_CFG_HCLK_DIV_16 = 0x7,
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};
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enum {
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STM32L4X_RCC_CFG_SYSCLK_DIV_0 = 0x0,
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STM32L4X_RCC_CFG_SYSCLK_DIV_2 = 0x8,
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STM32L4X_RCC_CFG_SYSCLK_DIV_4 = 0x9,
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STM32L4X_RCC_CFG_SYSCLK_DIV_8 = 0xa,
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STM32L4X_RCC_CFG_SYSCLK_DIV_16 = 0xb,
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STM32L4X_RCC_CFG_SYSCLK_DIV_64 = 0xc,
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STM32L4X_RCC_CFG_SYSCLK_DIV_128 = 0xd,
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STM32L4X_RCC_CFG_SYSCLK_DIV_256 = 0xe,
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STM32L4X_RCC_CFG_SYSCLK_DIV_512 = 0xf,
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};
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enum {
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STM32L4X_RCC_CFG_MCO_DIV_0 = 0x0,
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STM32L4X_RCC_CFG_MCO_DIV_2 = 0x1,
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STM32L4X_RCC_CFG_MCO_DIV_4 = 0x2,
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STM32L4X_RCC_CFG_MCO_DIV_8 = 0x3,
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STM32L4X_RCC_CFG_MCO_DIV_16 = 0x4,
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};
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/**
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* @brief Reset and Clock Control
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*/
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union __rcc_cr {
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uint32_t val;
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struct {
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uint32_t msion :1 __packed;
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uint32_t msirdy :1 __packed;
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uint32_t msipllen :1 __packed;
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uint32_t msirgsel :1 __packed;
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uint32_t msirange :4 __packed;
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uint32_t hsion :1 __packed;
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uint32_t hsikeron :1 __packed;
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uint32_t hsirdy :1 __packed;
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uint32_t hsiasfs :1 __packed;
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uint32_t rsvd__12_15 :4 __packed;
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uint32_t hseon :1 __packed;
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uint32_t hserdy :1 __packed;
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uint32_t hsebyp :1 __packed;
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uint32_t csson :1 __packed;
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uint32_t rsvd__20_23 :4 __packed;
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uint32_t pllon :1 __packed;
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uint32_t pllrdy :1 __packed;
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uint32_t pllsai1on :1 __packed;
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uint32_t pllsai1rdy :1 __packed;
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/*
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* SAI2 not present on L4x2, L431xx, STM32L433xx,
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* and STM32L443xx.
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*/
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uint32_t pllsai2on :1 __packed;
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uint32_t pllsai2rdy :1 __packed;
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uint32_t rsvd__30_31 :2 __packed;
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} bit;
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};
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union __rcc_cfgr {
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uint32_t val;
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struct {
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uint32_t sw :2 __packed;
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uint32_t sws :2 __packed;
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uint32_t hpre :4 __packed;
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uint32_t ppre1 :3 __packed;
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uint32_t ppre2 :3 __packed;
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uint32_t stopwuck :1 __packed;
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uint32_t rsvd__16_23 :8 __packed;
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uint32_t mcosel :3 __packed; /* 2 bits long on L4x{1,5,6} */
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uint32_t mcopre :3 __packed;
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uint32_t rsvd__31 :1 __packed;
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} bit;
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};
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union __rcc_pllcfgr {
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uint32_t val;
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struct {
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uint32_t pllsrc :2 __packed;
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uint32_t rsvd__2_3 :2 __packed;
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uint32_t pllm :3 __packed;
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uint32_t rsvd__7 :1 __packed;
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uint32_t plln :7 __packed;
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uint32_t rsvd__15 :1 __packed;
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uint32_t pllpen :1 __packed;
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uint32_t pllp :1 __packed;
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uint32_t rsvd__18_19 :2 __packed;
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uint32_t pllqen :1 __packed;
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uint32_t pllq :2 __packed;
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uint32_t rsvd__23 :1 __packed;
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uint32_t pllren :1 __packed;
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uint32_t pllr :2 __packed;
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uint32_t pllpdiv :5 __packed; /* Not present on L4x{1,5,6} */
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} bit;
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};
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struct stm32l4x_rcc {
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union __rcc_cr cr;
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uint32_t icscr;
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union __rcc_cfgr cfgr;
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union __rcc_pllcfgr pllcfgr;
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uint32_t pllsai1cfgr;
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uint32_t pllsai2cfgr;
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uint32_t cier;
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uint32_t cifr;
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uint32_t cicr;
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uint32_t rsvd_0;
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uint32_t ahb1rstr;
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uint32_t ahb2rstr;
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uint32_t ahb3rstr;
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uint32_t rsvd_1;
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uint32_t apb1rstr1;
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uint32_t apb1rstr2;
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uint32_t apb2rstr;
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uint32_t rsvd_2;
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uint32_t ahb1enr;
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uint32_t ahb2enr;
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uint32_t ahb3enr;
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uint32_t rsvd_3;
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uint32_t apb1enr1;
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uint32_t apb1enr2;
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uint32_t apb2enr;
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uint32_t rsvd_4;
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uint32_t ahb1smenr;
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uint32_t ahb2smenr;
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uint32_t ahb3smenr;
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uint32_t rsvd_5;
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uint32_t apb1smenr1;
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uint32_t apb1smenr2;
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uint32_t apb2smenr;
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uint32_t rsvd_6;
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uint32_t ccipr;
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uint32_t rsvd_7;
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uint32_t bdcr;
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uint32_t csr;
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};
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#endif /* _STM32L4X_CLOCK_H_ */
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