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zephyr/drivers/interrupt_controller/intc_swerv_pic.c
Tomasz Bursztyka 4dcfb5531c isr: Normalize usage of device instance through ISR 
The goal of this patch is to replace the 'void *' parameter by 'struct
device *' if they use such variable or just 'const void *' on all
relevant ISRs

This will avoid not-so-nice const qualifier tweaks when device instances
will be constant.

Note that only the ISR passed to IRQ_CONNECT are of interest here.

In order to do so, the script fix_isr.py below is necessary:

from pathlib import Path
import subprocess
import pickle
import mmap
import sys
import re
import os

cocci_template = """
@r_fix_isr_0
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
(
 const struct device *D = (const struct device *)P;
|
 const struct device *D = P;
)
 ...
}

@r_fix_isr_1
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
 const struct device *D;
 ...
(
 D = (const struct device *)P;
|
 D = P;
)
 ...
}

@r_fix_isr_2
@
type ret_type;
identifier A;
@@
-ret_type <!fn!>(void *A)
+ret_type <!fn!>(const void *A)
{
 ...
}

@r_fix_isr_3
@
const struct device *D;
@@
-<!fn!>((void *)D);
+<!fn!>(D);

@r_fix_isr_4
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
(
-const struct device *D = (const struct device *)P;
|
-const struct device *D = P;
)
 ...
}

@r_fix_isr_5
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
-const struct device *D;
...
(
-D = (const struct device *)P;
|
-D = P;
)
 ...
}
"""

def find_isr(fn):
    db = []
    data = None
    start = 0

    try:
        with open(fn, 'r+') as f:
            data = str(mmap.mmap(f.fileno(), 0).read())
    except Exception as e:
        return db

    while True:
        isr = ""
        irq = data.find('IRQ_CONNECT', start)
        while irq > -1:
            p = 1
            arg = 1
            p_o = data.find('(', irq)
            if p_o < 0:
                irq = -1
                break;

            pos = p_o + 1

            while p > 0:
                if data[pos] == ')':
                    p -= 1
                elif data[pos] == '(':
                    p += 1
                elif data[pos] == ',' and p == 1:
                    arg += 1

                if arg == 3:
                    isr += data[pos]

                pos += 1

            isr = isr.strip(',\\n\\t ')
            if isr not in db and len(isr) > 0:
                db.append(isr)

            start = pos
            break

        if irq < 0:
            break

    return db

def patch_isr(fn, isr_list):
    if len(isr_list) <= 0:
        return

    for isr in isr_list:
        tmplt = cocci_template.replace('<!fn!>', isr)
        with open('/tmp/isr_fix.cocci', 'w') as f:
            f.write(tmplt)

        cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn]

        subprocess.run(cmd)

def process_files(path):
    if path.is_file() and path.suffix in ['.h', '.c']:
        p = str(path.parent) + '/' + path.name
        isr_list = find_isr(p)
        patch_isr(p, isr_list)
    elif path.is_dir():
        for p in path.iterdir():
            process_files(p)

if len(sys.argv) < 2:
    print("You need to provide a dir/file path")
    sys.exit(1)

process_files(Path(sys.argv[1]))

And is run: ./fix_isr.py <zephyr root directory>

Finally, some files needed manual fixes such.

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00

238 lines
5.1 KiB
C
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/*
* Copyright (c) 2019 Western Digital Corporation or its affiliates
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT swerv_pic
/**
* @brief SweRV EH1 PIC driver
*/
#include <kernel.h>
#include <arch/cpu.h>
#include <init.h>
#include <sw_isr_table.h>
#define SWERV_PIC_MAX_NUM CONFIG_NUM_IRQS
#define SWERV_PIC_MAX_ID (SWERV_PIC_MAX_NUM + RISCV_MAX_GENERIC_IRQ)
#define SWERV_PIC_MAX_PRIO 16
#define SWERV_PIC_mpiccfg 0x3000
#define SWERV_PIC_meipl(s) (0x0 + (s)*4)
#define SWERV_PIC_meip(x) (0x1000 + (x)*4)
#define SWERV_PIC_meie(s) (0x2000 + (s)*4)
#define SWERV_PIC_meigwctrl(s) (0x4000 + (s)*4)
#define SWERV_PIC_meigwclr(s) (0x5000 + (s)*4)
#define SWERV_PIC_meivt "0xBC8"
#define SWERV_PIC_meipt "0xBC9"
#define SWERV_PIC_meicpct "0xBCA"
#define SWERV_PIC_meicidpl "0xBCB"
#define SWERV_PIC_meicurpl "0xBCC"
#define SWERV_PIC_meihap "0xFC8"
#define swerv_piccsr(csr) SWERV_PIC_##csr
#define swerv_pic_readcsr(csr, value) \
volatile("csrr %0, "swerv_piccsr(csr) : "=r" (value))
#define swerv_pic_writecsr(csr, value) \
volatile("csrw "swerv_piccsr(csr)", %0" :: "rK" (value))
static int save_irq;
static uint32_t swerv_pic_read(uint32_t reg)
{
return *(volatile uint32_t *)(DT_INST_REG_ADDR(0) + reg);
}
static void swerv_pic_write(uint32_t reg, uint32_t val)
{
*(volatile uint32_t *)(DT_INST_REG_ADDR(0) + reg) = val;
}
void swerv_pic_irq_enable(uint32_t irq)
{
uint32_t key;
if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) {
return;
}
key = irq_lock();
swerv_pic_write(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ), 1);
irq_unlock(key);
}
void swerv_pic_irq_disable(uint32_t irq)
{
uint32_t key;
if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) {
return;
}
key = irq_lock();
swerv_pic_write(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ), 0);
irq_unlock(key);
}
int swerv_pic_irq_is_enabled(uint32_t irq)
{
if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) {
return -1;
}
return swerv_pic_read(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ))
& 0x1;
}
void swerv_pic_set_priority(uint32_t irq, uint32_t priority)
{
uint32_t key;
if (irq <= RISCV_MAX_GENERIC_IRQ) {
return;
}
if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) {
return;
}
if (priority >= SWERV_PIC_MAX_PRIO) {
return;
}
key = irq_lock();
swerv_pic_write(SWERV_PIC_meipl(irq - RISCV_MAX_GENERIC_IRQ), priority);
irq_unlock(key);
}
int swerv_pic_get_irq(void)
{
return save_irq;
}
static void swerv_pic_irq_handler(const void *arg)
{
uint32_t tmp;
uint32_t irq;
struct _isr_table_entry *ite;
/* trigger the capture of the interrupt source ID */
__asm__ swerv_pic_writecsr(meicpct, 0);
__asm__ swerv_pic_readcsr(meihap, tmp);
irq = (tmp >> 2) & 0xff;
save_irq = irq;
if (irq == 0U || irq >= 64) {
z_irq_spurious(NULL);
}
irq += RISCV_MAX_GENERIC_IRQ;
/* Call the corresponding IRQ handler in _sw_isr_table */
ite = (struct _isr_table_entry *)&_sw_isr_table[irq];
if (ite->isr)
ite->isr(ite->arg);
swerv_pic_write(SWERV_PIC_meigwclr(irq), 0);
}
static int swerv_pic_init(const struct device *dev)
{
ARG_UNUSED(dev);
int i;
/* Init priority order to 0, 0=lowest to 15=highest */
swerv_pic_write(SWERV_PIC_mpiccfg, 0);
/* Ensure that all interrupts are disabled initially */
for (i = 1; i < SWERV_PIC_MAX_ID; i++) {
swerv_pic_write(SWERV_PIC_meie(i), 0);
}
/* Set priority of each interrupt line to 0 initially */
for (i = 1; i < SWERV_PIC_MAX_ID; i++) {
swerv_pic_write(SWERV_PIC_meipl(i), 15);
}
/* Set property of each interrupt line to level-triggered/high */
for (i = 1; i < SWERV_PIC_MAX_ID; i++) {
swerv_pic_write(SWERV_PIC_meigwctrl(i), (0<<1)|(0<<0));
}
/* clear pending of each interrupt line */
for (i = 1; i < SWERV_PIC_MAX_ID; i++) {
swerv_pic_write(SWERV_PIC_meigwclr(i), 0);
}
/* No interrupts masked */
__asm__ swerv_pic_writecsr(meipt, 0);
__asm__ swerv_pic_writecsr(meicidpl, 0);
__asm__ swerv_pic_writecsr(meicurpl, 0);
/* Setup IRQ handler for SweRV PIC driver */
IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,
0,
swerv_pic_irq_handler,
NULL,
0);
/* Enable IRQ for SweRV PIC driver */
irq_enable(RISCV_MACHINE_EXT_IRQ);
return 0;
}
void arch_irq_enable(unsigned int irq)
{
uint32_t mie;
if (irq > RISCV_MAX_GENERIC_IRQ) {
swerv_pic_irq_enable(irq);
return;
}
/*
* CSR mie register is updated using atomic instruction csrrs
* (atomic read and set bits in CSR register)
*/
__asm__ volatile ("csrrs %0, mie, %1\n"
: "=r" (mie)
: "r" (1 << irq));
}
void arch_irq_disable(unsigned int irq)
{
uint32_t mie;
if (irq > RISCV_MAX_GENERIC_IRQ) {
swerv_pic_irq_disable(irq);
return;
}
/*
* Use atomic instruction csrrc to disable device interrupt in mie CSR.
* (atomic read and clear bits in CSR register)
*/
__asm__ volatile ("csrrc %0, mie, %1\n"
: "=r" (mie)
: "r" (1 << irq));
};
int arch_irq_is_enabled(unsigned int irq)
{
uint32_t mie;
if (irq > RISCV_MAX_GENERIC_IRQ)
return swerv_pic_irq_is_enabled(irq);
__asm__ volatile ("csrr %0, mie" : "=r" (mie));
return !!(mie & (1 << irq));
}
SYS_INIT(swerv_pic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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