2e2ad8166e
Setting up new platforms to handle emulation, and make them the only ones able to run on QEMU from the Makefile "qemu" target to avoid confusion with other platforms. We have now platform qemu_x86 and platform qemu_cortex_m3, also modification to the sanity checks to have qemu support only on those platforms Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com> Change-Id: I9291918a1d58fea4f37750ada78234628f9a5d98 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
/* board.h - board configuration macros for the QEMU for arm platform */
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/*
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* Copyright (c) 2013-2015 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* DESCRIPTION
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* This header file is used to specify and describe board-level aspects for
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* the 'QEMU' platform.
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*/
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#ifndef _BOARD__H_
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#define _BOARD__H_
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#include <misc/util.h>
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/* default system clock */
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#define SYSCLK_DEFAULT_IOSC_HZ MHZ(12)
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/* address bases */
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#define PERIPH_ADDR_BASE_UART0 0x4000C000
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#define PERIPH_ADDR_BASE_UART1 0x4000D000
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#define PERIPH_ADDR_BASE_UART2 0x4000E000
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/* IRQs */
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#define IRQ_GPIO_PORTA 0
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#define IRQ_GPIO_PORTB 1
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#define IRQ_GPIO_PORTC 2
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#define IRQ_GPIO_PORTD 3
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#define IRQ_GPIO_PORTE 4
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#define IRQ_UART0 5
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#define IRQ_UART1 6
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#define IRQ_SSI0 7
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#define IRQ_I2C0 8
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#define IRQ_PWM_FAULT 9
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#define IRQ_PWM_GEN0 10
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#define IRQ_PWM_GEN1 11
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#define IRQ_PWM_GEN2 12
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#define IRQ_QEI0 13
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#define IRQ_ADC0_SEQ0 14
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#define IRQ_ADC0_SEQ1 15
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#define IRQ_ADC0_SEQ2 16
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#define IRQ_ADC0_SEQ3 17
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#define IRQ_WDOG0 18
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#define IRQ_TIMER0A 19
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#define IRQ_TIMER0B 20
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#define IRQ_TIMER1A 21
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#define IRQ_TIMER1B 22
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#define IRQ_TIMER2A 23
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#define IRQ_TIMER2B 24
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#define IRQ_ANALOG_COMP0 25
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#define IRQ_ANALOG_COMP1 26
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#define IRQ_RESERVED0 27
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#define IRQ_SYS_CONTROL 28
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#define IRQ_FLASH_MEM_CTRL 29
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#define IRQ_GPIO_PORTF 30
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#define IRQ_GPIO_PORTG 31
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#define IRQ_RESERVED1 32
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#define IRQ_UART2 33
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#define IRQ_RESERVED2 34
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#define IRQ_TIMER3A 35
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#define IRQ_TIMER3B 36
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#define IRQ_I2C1 37
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#define IRQ_QEI1 38
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#define IRQ_RESERVED3 39
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#define IRQ_RESERVED4 40
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#define IRQ_RESERVED5 41
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#define IRQ_ETH 42
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#define IRQ_HIBERNATION 43
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#ifndef _ASMLANGUAGE
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#include <device.h>
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#include <misc/util.h>
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#include <drivers/rand32.h>
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/* uart configuration settings */
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#define UART_IRQ_FLAGS 0
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#endif /* !_ASMLANGUAGE */
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#endif /* _BOARD__H_ */
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