zephyr/soc/xtensa
Daniel Leung 2d5c724ed8 Revert "soc: intel_adsp: fix linker script for cavs_v20"
This reverts commit 3cc14b2c2b.

Revert this due to the same reason as commit
a29b66bbf5:

  Unfortunately this mechanism doesn't seem to actually work on the SDK
  linker.  The emitted sections, when passed a symbol name as the "start
  address" just appear wherever the "." variable was pointing (in this
  case, into the cached region).  That breaks the kernel coherence
  layer, obviously.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-11-16 10:13:46 -05:00
..
esp32 soc: esp32: soc does not support 2 cores 2021-10-23 20:44:26 -04:00
esp32s2 clock: esp32: unify clock control for all espressif socs 2021-11-04 15:21:26 -04:00
intel_adsp Revert "soc: intel_adsp: fix linker script for cavs_v20" 2021-11-16 10:13:46 -05:00
intel_s1000 Revert "linker: xtensa: move IDT_LIST region" 2021-09-08 20:29:53 -05:00
nxp_adsp soc: xtensa: adsp: add support for NXP ADSP for i.MX8MP 2021-10-20 19:08:50 -04:00
sample_controller linker: align _image_text_start/end/size linker symbols name 2021-08-28 08:48:03 -04:00
CMakeLists.txt soc/xtensa/intel_adsp: Upstream updates 2020-10-21 06:38:53 -04:00