2b441732ff
The current GIC driver implementation only supports the GIC-400, which implements the GICv2 interface. This commit refactors the GIC driver to support multiple GIC versions and adds GICv1 interface support (GICv1 and GICv2 interfaces are very similar). Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
199 lines
3.7 KiB
C
199 lines
3.7 KiB
C
/*
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* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_GIC_H_
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#define ZEPHYR_INCLUDE_DRIVERS_GIC_H_
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#include <arch/cpu.h>
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/*
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* GIC Register Interface Base Addresses
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*/
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#define GIC_DIST_BASE DT_INST_0_ARM_GIC_BASE_ADDRESS_0
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#define GIC_CPU_BASE DT_INST_0_ARM_GIC_BASE_ADDRESS_1
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/*
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* GIC Distributor Interface
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*/
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/*
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* 0x000 Distributor Control Register
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* v1 ICDDCR
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* v2/v3 GICD_CTLR
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*/
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#define GICD_CTLR (GIC_DIST_BASE + 0x0)
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/*
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* 0x004 Interrupt Controller Type Register
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* v1 ICDICTR
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* v2/v3 GICD_TYPER
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*/
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#define GICD_TYPER (GIC_DIST_BASE + 0x4)
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/*
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* 0x008 Distributor Implementer Identification Register
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* v1 ICDIIDR
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* v2/v3 GICD_IIDR
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*/
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#define GICD_IIDR (GIC_DIST_BASE + 0x8)
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/*
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* 0x080 Interrupt Group Registers
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* v1 ICDISRn
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* v2/v3 GICD_IGROUPRn
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*/
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#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
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/*
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* 0x100 Interrupt Set-Enable Reigsters
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* v1 ICDISERn
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* v2/v3 GICD_ISENABLERn
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*/
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#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
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/*
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* 0x180 Interrupt Clear-Enable Registers
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* v1 ICDICERn
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* v2/v3 GICD_ICENABLERn
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*/
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#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
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/*
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* 0x200 Interrupt Set-Pending Registers
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* v1 ICDISPRn
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* v2/v3 GICD_ISPENDRn
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*/
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#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
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/*
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* 0x280 Interrupt Clear-Pending Registers
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* v1 ICDICPRn
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* v2/v3 GICD_ICPENDRn
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*/
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#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
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/*
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* 0x300 Interrupt Set-Active Registers
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* v1 ICDABRn
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* v2/v3 GICD_ISACTIVERn
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*/
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#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
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#if CONFIG_GIC_VER >= 2
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/*
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* 0x380 Interrupt Clear-Active Registers
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* v2/v3 GICD_ICACTIVERn
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*/
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#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
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#endif
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/*
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* 0x400 Interrupt Priority Registers
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* v1 ICDIPRn
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* v2/v3 GICD_IPRIORITYRn
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*/
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#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
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/*
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* 0x800 Interrupt Processor Targets Registers
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* v1 ICDIPTRn
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* v2/v3 GICD_ITARGETSRn
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*/
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#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
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/*
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* 0xC00 Interrupt Configuration Registers
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* v1 ICDICRn
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* v2/v3 GICD_ICFGRn
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*/
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#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
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/*
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* 0xF00 Software Generated Interrupt Register
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* v1 ICDSGIR
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* v2/v3 GICD_SGIR
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*/
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#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
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/*
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* GIC CPU Interface
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*/
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#if CONFIG_GIC_VER <= 2
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/*
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* 0x0000 CPU Interface Control Register
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* v1 ICCICR
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* v2/v3 GICC_CTLR
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*/
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#define GICC_CTLR (GIC_CPU_BASE + 0x0)
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/*
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* 0x0004 Interrupt Priority Mask Register
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* v1 ICCPMR
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* v2/v3 GICC_PMR
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*/
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#define GICC_PMR (GIC_CPU_BASE + 0x4)
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/*
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* 0x0008 Binary Point Register
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* v1 ICCBPR
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* v2/v3 GICC_BPR
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*/
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#define GICC_BPR (GIC_CPU_BASE + 0x8)
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/*
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* 0x000C Interrupt Acknowledge Register
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* v1 ICCIAR
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* v2/v3 GICC_IAR
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*/
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#define GICC_IAR (GIC_CPU_BASE + 0xc)
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/*
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* 0x0010 End of Interrupt Register
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* v1 ICCEOIR
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* v2/v3 GICC_EOIR
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*/
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#define GICC_EOIR (GIC_CPU_BASE + 0x10)
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/*
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* Helper Constants
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*/
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#define GIC_SPI_INT_BASE 32
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/* GICC_CTLR */
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#define GICC_CTLR_ENABLEGRP0 BIT(0)
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#define GICC_CTLR_ENABLEGRP1 BIT(1)
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#define GICC_CTLR_ENABLE_MASK (GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1)
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#if defined(CONFIG_GIC_V2)
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#define GICC_CTLR_FIQBYPDISGRP0 BIT(5)
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#define GICC_CTLR_IRQBYPDISGRP0 BIT(6)
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#define GICC_CTLR_FIQBYPDISGRP1 BIT(7)
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#define GICC_CTLR_IRQBYPDISGRP1 BIT(8)
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#define GICC_CTLR_BYPASS_MASK (GICC_CTLR_FIQBYPDISGRP0 | \
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GICC_CTLR_IRQBYPDISGRP1 | \
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GICC_CTLR_FIQBYPDISGRP1 | \
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GICC_CTLR_IRQBYPDISGRP1)
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#endif /* CONFIG_GIC_V2 */
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/* GICC_IAR */
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#define GICC_IAR_SPURIOUS 1023
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/* GICC_ICFGR */
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#define GICC_ICFGR_MASK BIT_MASK(2)
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#define GICC_ICFGR_TYPE BIT(1)
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#endif /* CONFIG_GIC_VER <= 2 */
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#endif /* ZEPHYR_INCLUDE_DRIVERS_GIC_H_ */
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