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zephyr/soc/xtensa/intel_adsp
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Guennadi Liakhovetski 2a6c70ab19 cavs_v25: switch over to Tigerlake H configuration 
Tigerlake H has less RAM and fewer cores. Both should be
supported, selectable at the board level. For now use the H
configuration as more readily available for testing.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2021-01-11 16:10:23 -05:00
..
cavs_v15 rimage: update rimage: add configuration and extended manifest 2021-01-11 16:10:23 -05:00
cavs_v18 cavs_v18, v20, v25: calculate trace base address correctly 2021-01-11 16:10:23 -05:00
cavs_v20 cavs_v18, v20, v25: calculate trace base address correctly 2021-01-11 16:10:23 -05:00
cavs_v25 cavs_v25: switch over to Tigerlake H configuration 2021-01-11 16:10:23 -05:00
common xtensa: IPM is only required if SMP is enabled 2021-01-11 16:10:23 -05:00
CMakeLists.txt xtensa: set toolchain variant per SoC 2020-12-20 14:30:50 -05:00
Kconfig arch/xtensa: soc/xtensa/intel_adsp: Enable KERNEL_COHERENCE 2020-10-21 06:38:53 -04:00
Kconfig.defconfig soc/xtensa/intel_adsp: Upstream updates 2020-10-21 06:38:53 -04:00
Kconfig.soc soc/xtensa/intel_adsp: Upstream updates 2020-10-21 06:38:53 -04:00